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| S1D13806 Embedded Memory Display Controller .D at Sh a et e 4U . om c MSC Vertriebs-GmbH Productmarketing Displays & Systems Friedrich-Bergius-Str. 9, D - 65203 Wiesbaden Tel:+49-611-97320-0, Fax:+49-61197320-88 http://www.msc-ge.com w w w Hardware Functional Specification Document Number: X28B-A-001-12 w w w .D t a S a e h t e U 4 .c m o Copyright (c) 2001, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. w w w .D at Sh a et e 4U . om c Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 17 Pins . . . . . . . . . . . . . . . . . 4.1 Pinout Diagram . . . . . . . . 4.2 Pin Description . . . . . . . . 4.2.1 Host Interface . . . . . . . . 4.2.2 LCD Interface . . . . . . . . 4.2.3 MediaPlug Interface . . . . . 4.2.4 CRT Interface . . . . . . . . 4.2.5 General Purpose IO . . . . . 4.2.6 Configuration . . . . . . . . 4.2.7 Miscellaneous . . . . . . . . 4.3 Summary of Configuration Options 4.4 Multiple Function Pin Mapping . 4.5 LCD Interface Pin Mapping . . . 4.6 CRT/TV Interface . . . . . . . D.C. Characteristics . . . . . . . . . . . . . . ... .. .. ... ... ... ... ... ... ... .. .. .. .. . . . . . . . . . . . . . . ...... ..... ..... ....... ....... ....... ....... ....... ....... ....... ..... ..... ..... ..... . . . . . . . . . . . . . . ....... ...... ...... ........ ........ ........ ........ ........ ........ ........ ...... ...... ...... ...... ... .. .. ... ... ... ... ... ... ... .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. ... ... ... ... ... ... ... .. .. .. .. 22 22 24 24 30 30 31 31 32 32 33 34 35 36 2 3 4 5 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 .... .... .... .... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... .... ..... 39 39 41 42 42 44 46 48 50 52 54 56 58 60 62 62 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Generic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx) . . . . . . . . . . . . . . 6.3.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . 6.3.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . . 6.3.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) 6.3.8 PC Card Timing (e.g. StrongARM) . . . . . . . . . . . . . . . . . . . . . 6.3.9 Philips Interface Timing (e.g. PR31500/PR31700) . . . . . . . . . . . . . 6.3.10 Toshiba Interface Timing (e.g. TX39xx) . . . . . . . . . . . . . . . . . . 6.4 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 4 Epson Research and Development Vancouver Design Center 6.4.2 Power Save Status . . . . . . . . . . . . . . . . 6.5 Display Interface . . . . . . . . . . . . . . . 6.5.1 Single Monochrome 4-Bit Panel Timing . . . . 6.5.2 Single Monochrome 8-Bit Panel Timing . . . . 6.5.3 Single Color 4-Bit Panel Timing . . . . . . . . 6.5.4 Single Color 8-Bit Panel Timing (Format 1) . . 6.5.5 Single Color 8-Bit Panel Timing (Format 2) . . 6.5.6 Single Color 16-Bit Panel Timing . . . . . . . . 6.5.7 Dual Monochrome 8-Bit Panel Timing . . . . . 6.5.8 Dual Color 8-Bit Panel Timing . . . . . . . . . 6.5.9 Dual Color 16-Bit Panel Timing . . . . . . . . 6.5.10 TFT/D-TFD Panel Timing . . . . . . . . . . . . 6.5.11 CRT Timing . . . . . . . . . . . . . . . . . . . 6.6 TV Timing . . . . . . . . . . . . . . . . . 6.6.1 TV Output Timing . . . . . . . . . . . . . . . . 6.7 MediaPlug Interface Timing . . . . . . . . . . 7 Clocks . . . . . . . . . . . 7.1 Clock Overview . . . 7.2 Clock Descriptions . . 7.2.1 MCLK . . . . . . 7.2.2 LCD PCLK . . . 7.2.3 CRT/TV PCLK . 7.2.4 MediaPlug Clock 7.3 Clock Selection . . . 7.4 Clocks vs. Functions . . . . . . . . . . ....... ...... ...... ........ ........ ........ ........ ...... ...... . . . . . . . . . . . . . . ... .. .. ... ... ... ... .. .. ... .. ... ... .. .. .. ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. ... ... ... ... ... ... ... ... ... ... ... .. ... .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. ... ... ... ... ... ... ... ... ... ... ... .. ... .. . . . . . . . . . . . . . . . . ... .. ... ... ... ... ... ... ... ... ... ... ... .. ... .. . . . . . . . . . . . . . . . . ... .. ... ... ... ... ... ... ... ... ... ... ... .. ... .. . . . . . . . . . . . . . . . . . . 63 . .64 . . 64 . . 66 . . 68 . . 70 . . 72 . . 74 . . 76 . . 78 . . 80 . . 82 . . 85 . .87 . . 87 . . 91 . . . . . . . . . . . . . . . . . . . . . . . . 92 . 92 .93 . 93 . 93 . 93 . 93 . 94 .95 . 96 . 96 . 96 . 96 . 97 . 98 101 .101 .102 .103 .103 .108 .110 .115 ...... ..... ..... ....... ....... ....... ....... ..... ..... ...... ..... ....... ....... ..... ..... ..... ....... ....... ....... ....... ....... ....... ....... ........... ......... ......... ............ ............ ............ ............ ......... ......... ........... ......... ............ ............ ......... ......... ......... ............ ............ ............ ............ ............ ............ ............ 8 Registers . . . . . . . . . . . . . . . . 8.1 Initializing the S1D13806 . . . . . 8.1.1 Register Memory Select Bit . . . 8.1.2 SDRAM Initialization Bit . . . . 8.2 Register Mapping . . . . . . . . 8.3 Register Set . . . . . . . . . . . 8.4 Register Descriptions . . . . . . . 8.4.1 Basic Registers . . . . . . . . . 8.4.2 General IO Pins Registers . . . . 8.4.3 Configuration Readback Register 8.4.4 Clock Configuration Registers . 8.4.5 Memory Configuration Registers 8.4.6 Panel Configuration Registers . . 8.4.7 LCD Display Mode Registers . . S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 5 8.4.8 CRT/TV Configuration Registers . . 8.4.9 CRT/TV Display Mode Registers . . 8.4.10 LCD Ink/Cursor Registers . . . . . . 8.4.11 CRT/TV Ink/Cursor Registers . . . 8.4.12 BitBLT Configuration Registers . . 8.4.13 Look-Up Table Registers . . . . . . 8.4.14 Power Save Configuration Registers 8.4.15 Miscellaneous Registers . . . . . . . 8.4.16 Common Display Mode Register . . 8.5 MediaPlug Registers Descriptions . . . 8.5.1 MediaPlug Control Registers . . . . 8.5.2 MediaPlug Data Registers . . . . . . 8.6 BitBLT Data Registers Descriptions . . . 9 . . . . . . . . . . . . . ... ... ... ... ... ... ... ... ... .. ... ... .. . . . . . . . . . . . . . ... ... ... ... ... ... ... ... ... .. ... ... .. . . . . . . . . . . . . . ... ... ... ... ... ... ... ... ... .. ... ... .. . . . . . . . . . . . . . ... ... ... ... ... ... ... ... ... .. ... ... .. . . . . . . . . . . . . . ... ... ... ... ... ... ... ... ... .. ... ... .. . . . . . . . . . . . . . ... ... ... ... ... ... ... ... ... .. ... ... .. .120 .125 .128 .132 .137 .145 .146 .148 .149 . 150 .150 .155 . 155 2D BitBLT Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9.2 BitBLT Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . . 157 . 158 . 158 . 158 10 Display Buffer . . . . . . . . . . . . . 10.1 Image Buffer . . . . . . . . . . 10.2 Ink Layer/Hardware Cursor Buffers . 10.3 Dual Panel Buffer . . . . . . . . 11 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13 TV Considerations . . . . . . . . . . . . . . . . . . . . 13.1 NTSC/PAL Operation . . . . . . . . . . . . . . 13.2 Clock Source . . . . . . . . . . . . . . . . . . 13.3 Filters . . . . . . . . . . . . . . . . . . . . 13.3.1 Chrominance Filter (REG[05Bh] bit 5) . . . . . . . 13.3.2 Luminance Filter (REG[05Bh] bit 4) . . . . . . . . 13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1]) . . . . . 13.4 TV Output Levels . . . . . . . . . . . . . . . . 13.4.1 TV Image Display and Positioning . . . . . . . . . 13.4.2 TV Cursor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ...... ...... ...... ........ ........ ........ ...... ........ ........ ... .. .. .. ... ... ... .. ... ... . . . . . . . . . . . . . 165 . . . 165 . . . 165 . . . 166 . . . .166 . . . .166 . . . . 166 . . . 167 . . . .170 . . . .172 14 Ink Layer/Hardware Cursor Architecture . . . . . . . . . . . . . . . . . . . . . . . 173 14.1 Ink Layer/Hardware Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . 173 14.2 Ink/Cursor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 6 Epson Research and Development Vancouver Design Center 14.3 Ink/Cursor Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . 175 14.3.1 Ink Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 14.3.2 Cursor Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15 SwivelViewTM . . . . . . . . . . . . . . 15.1 Concept . . . . . . . . . . . . 15.2 90 SwivelView . . . . . . . . . 15.2.1 Register Programming . . . . . . 15.2.2 Physical Memory Requirement . 15.2.3 Limitations . . . . . . . . . . . . 15.3 180 SwivelView . . . . . . . . . 15.3.1 Register Programming . . . . . . 15.3.2 Physical Memory Requirement . 15.3.3 Limitations . . . . . . . . . . . . 15.4 270 SwivelView . . . . . . . . . 15.4.1 Register Programming . . . . . . 15.4.2 Physical Memory Requirement . 15.4.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. ... ... ... .. ... ... ... .. ... ... ... . . . . . . . . . . . . . . ...... ..... ..... ....... ....... ....... ..... ....... ....... ....... ..... ....... ....... ....... .... ... ... ... ... .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ...... ...... ........ ........ ........ ...... ........ ........ ........ ...... ........ ........ ........ . . . . . . . . .... ... ... ... .... ... ... ... . . . . . . . . . . . . . . . . ... .. .. ... ... ... .. ... ... ... .. ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 177 177 .178 .179 .182 182 .182 .183 .183 183 .184 .185 .185 186 186 186 187 188 188 188 188 16 EPSON Independent Simultaneous Display (EISD) 16.1 Registers . . . . . . . . . . . . . . . . . . 16.2 Display Mapping . . . . . . . . . . . . . . . 16.3 Bandwidth Limitation . . . . . . . . . . . . . 17 MediaPlug Interface . . . . . . . . . 17.1 Revision Code . . . . . . . . . 17.2 How to enable the MediaPlug Slave 17.3 MediaPlug Interface Pin Mapping . . . . . . . . . ... .. .. .. . . . . . . . . . . . . .... ... ... ... .... ... ... ... . . . . . . . . . . . . . . 18 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . 18.1.1 LCD Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.2 CRT Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.3 TV Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Example Frame Rates . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1 Frame Rates for 640x480 with EISD Disabled . . . . . . . . . . . . . . . . . 18.2.2 Frame Rates for 800x600 with EISD Disabled . . . . . . . . . . . . . . . . . 18.2.3 Frame Rates for 1024x768 with EISD Disabled . . . . . . . . . . . . . . . . 18.2.4 Frame Rates for LCD and CRT (640x480) with EISD Enabled . . . . . . . . 18.2.5 Frame Rates for LCD and CRT (800x600) with EISD Enabled . . . . . . . . 18.2.6 Frame Rates for LCD and CRT (1024x768) with EISD Enabled . . . . . . . . 18.2.7 Frame Rates for LCD and NTSC TV with EISD Enabled . . . . . . . . . . . 18.2.8 Frame Rates for LCD and PAL TV with EISD Enabled . . . . . . . . . . . . . 189 . 189 . .189 . .190 . .191 . 192 . .192 . .194 . .195 . .196 . .198 . .199 . .200 . .201 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 7 19 Power Save Mode . . . . . . . . 19.1 Overview . . . . . . . . 19.2 Power Save Status Bits . . . 19.3 Power Save Mode Summary . . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . . 202 . 202 . 202 . 203 20 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 22 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 9 List of Tables Table 2-1 : S1D13806 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-1: PFBGA 220-pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-2 : Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-3 : LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-4 : MediaPlug Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-5 : CRT Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-6 : General Purpose IO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-7 : Configuration Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-8 : Miscellaneous Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-9 : Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-10 : CPU Interface Pin Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4-11 : LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5-1 : Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5-2 : Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5-3 : Electrical Characteristics for VDD = 3.3V typical. . . . . . . . . . . . . . . . . . . . . Table 6-1 : Clock Input Requirements for BUSCLK, CLKI, CLKI2, and CLKI3 When Not Divided Table 6-2 : Clock Input Requirements for MCLK Source when Source Divided . . . . . . . . . . . Table 6-3 : Clock Input Requirements for LCD PCLK, CRT/TV PCLK, or MediaPlug Source when Source Divided . . . . . . . . . . . . . . . . . . . . . . . . Table 6-4: Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-5 : Generic Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-6 : Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-7 : Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-8 : MIPS/ISA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-9 : Motorola MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-10 : Motorola MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . Table 6-11 : Motorola PowerPC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-12: PC Card Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-13 : Philips Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-14 : Toshiba Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-15 : LCD Panel Power-off/Power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-16 : Power Save Status and Local Bus Memory Access Relative to Power Save Mode . . . Table 6-17 : SDRAM Refresh Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-18 : Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . Table 6-19 : Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . Table 6-20 : Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-21 : Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . 16 23 24 30 30 31 31 32 32 33 34 35 37 37 38 39 40 40 41 43 45 47 49 51 53 55 57 59 61 62 63 63 65 67 69 71 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 10 Epson Research and Development Vancouver Design Center Table 6-22 : Single Color 8-Bit Panel A.C. Timing (Format 2) Table 6-23 : Single Color 16-Bit Panel A.C. Timing . . . . . . Table 6-24 : Dual Monochrome 8-Bit Panel A.C. Timing . . . Table 6-25 : Dual Color 8-Bit Panel A.C. Timing . . . . . . . Table 6-26 : Dual Color 16-Bit Panel A.C. Timing. . . . . . . Table 6-27 : TFT/D-TFD A.C. Timing . . . . . . . . . . . . . Table 6-28 : CRT A.C. Timing . . . . . . . . . . . . . . . . . Table 6-29 : Horizontal Timing for NTSC/PAL . . . . . . . . Table 6-30 : Vertical Timing for NTSC/PAL. . . . . . . . . . Table 6-31: MediaPlug A.C. Timing . . . . . . . . . . . . . . Table 7-1 : Clock Selection . . . . . . . . . . . . . . . . . . . Table 7-2: Clocks vs. Functions . . . . . . . . . . . . . . . . Table 8-1 : Register Mapping with CS# = 0 and M/R# = 0 . . Table 8-2 : S1D13806 Register Set . . . . . . . . . . . . . . . Table 8-3 : Media Plug/GPIO12 Pin Functionality . . . . . . . Table 8-4 : MCLK Source Select . . . . . . . . . . . . . . . . Table 8-5 : LCD PCLK Divide Selection. . . . . . . . . . . . Table 8-6 : LCD PCLK Source Selection. . . . . . . . . . . . Table 8-7 : CRT/TV PCLK Divide Selection. . . . . . . . . . Table 8-8 : CRT/TV PCLK Source Selection . . . . . . . . . Table 8-9 : MediaPlug Clock Divide Selection. . . . . . . . . Table 8-10 : MediaPlug Clock Source Selection . . . . . . . . Table 8-11 : Minimum Memory Timing Selection . . . . . . . Table 8-12 : SDRAM Refresh Rate Selection . . . . . . . . . Table 8-13 : SDRAM Timings Control Register Settings . . . Table 8-14 : Panel Data Width Selection . . . . . . . . . . . . Table 8-15: Horizontal Display Width (Pixels) . . . . . . . . . Table 8-16 : LCD FPLINE Polarity Selection . . . . . . . . . Table 8-17 : LCD FPFRAME Polarity Selection . . . . . . . . Table 8-18: Setting SwivelView Modes . . . . . . . . . . . . Table 8-19 : LCD Bit-per-pixel Selection . . . . . . . . . . . Table 8-20 : LCD Pixel Panning Selection . . . . . . . . . . . Table 8-21: DAC Output Level Selection . . . . . . . . . . . Table 8-22 : CRT/TV Bit-per-pixel Selection . . . . . . . . . Table 8-23 : CRT/TV Pixel Panning Selection . . . . . . . . . Table 8-24 : LCD Ink/Cursor Selection. . . . . . . . . . . . . Table 8-25 : LCD Ink/Cursor Start Address Encoding . . . . . Table 8-26 : CRT/TV Ink/Cursor Selection . . . . . . . . . . Table 8-27 : CRT/TV Ink/Cursor Start Address Encoding . . . Table 8-28 : BitBLT Active Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 . 75 . 77 . 79 . 81 . 84 . 86 . 89 . 90 . 91 . 94 . 95 . 97 . 98 .102 .104 .104 .105 .105 .106 .106 .107 .107 .109 .109 .110 .111 .113 .115 .116 .116 .119 .124 .125 .127 .128 .129 .132 .133 .137 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 11 Table 8-29: BitBLT FIFO Words Available . . . . . . . . . . . . . . . . . . Table 8-30 : BitBLT ROP Code/Color Expansion Function Selection. . . . . Table 8-31 : BitBLT Operation Selection . . . . . . . . . . . . . . . . . . . Table 8-32 : BitBLT Source Start Address Selection . . . . . . . . . . . . . Table 8-33 : LUT Mode Selection . . . . . . . . . . . . . . . . . . . . . . . Table 8-34: Setting SwivelView Modes . . . . . . . . . . . . . . . . . . . . Table 8-35: Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . Table 8-36: MediaPlug LCMD Read/Write Descriptions . . . . . . . . . . . Table 8-37: Timeout Option Delay . . . . . . . . . . . . . . . . . . . . . . . Table 8-38: Cable Detect and Remote Powered Status. . . . . . . . . . . . . Table 8-39: MediaPlug CMD Read/Write Descriptions . . . . . . . . . . . . Table 8-40: MediaPlug Commands. . . . . . . . . . . . . . . . . . . . . . . Table 10-1 : S1D13806 Addressing . . . . . . . . . . . . . . . . . . . . . . Table 13-1 : Required Clock Frequencies for NTSC/PAL . . . . . . . . . . . Table 13-2 : NTSC/PAL SVideo-Y (Luminance) Output Levels . . . . . . . Table 13-3 : NTSC/PAL SVideo-C (Chrominance) Output Levels . . . . . . Table 13-4 : NTSC/PAL Composite Output Levels . . . . . . . . . . . . . . Table 13-5 : Minimum and Maximum Values for NTSC/PAL TV . . . . . . Table 13-6 : Register Values for Example NTSC/PAL Images . . . . . . . . Table 14-1 : Ink/Cursor Start Address Encoding . . . . . . . . . . . . . . . . Table 14-2 : Ink/Cursor Color Select . . . . . . . . . . . . . . . . . . . . . . Table 15-1 : Memory Size Required for SwivelView 90 and 270 . . . . . . Table 17-1: MediaPlug Interface Pin Mapping . . . . . . . . . . . . . . . . . Table 18-1: Frame Rates for 640x480 with EISD Disabled . . . . . . . . . . Table 18-2: Frame Rates for 800x600 with EISD Disabled . . . . . . . . . . Table 18-3: Frame Rates for 1024x768 with EISD Disabled . . . . . . . . . Table 18-4: Frame Rates for LCD and CRT (640x480) with EISD Enabled . Table 18-5: Frame Rates for LCD and CRT (800x600) with EISD Enabled . Table 18-6: Frame Rates for LCD and CRT (1024x768) with EISD Enabled . Table 18-7: Frame Rates for LCD and NTSC TV with EISD Enabled . . . . Table 18-8: Frame Rates for LCD and PAL TV with EISD Enabled . . . . . Table 19-1: Power Save Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 . 139 .140 .141 .145 .149 .149 .150 .151 .151 .153 .154 .157 .165 .167 . 168 .169 . 171 .172 .173 .174 . 181 .188 . 192 . 194 . 195 . 196 . 198 . 199 . 200 . 201 .203 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 13 List of Figures Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: Figure 4-1: Figure 4-2: Figure 4-3: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 6-7: Figure 6-8: Figure 6-9: Figure 6-10: Figure 6-11: Figure 6-12: Figure 6-13: Figure 6-14: Figure 6-15: Figure 6-16: Figure 6-17: Figure 6-18: Figure 6-19: Figure 6-20: Figure 6-21: Figure 6-22: Figure 6-23: Figure 6-24: Typical System Diagram (Generic Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical System Diagram (Hitachi SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . . 17 Typical System Diagram (Hitachi SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . . 18 Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000) . . . . . . . . . . . . 18 Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030) . . . . . . . . . . . . 19 Typical System Diagram (Motorola Power PC Bus) . . . . . . . . . . . . . . . . . . . . 19 Typical System Diagram (NEC MIPS VR41xx Bus) . . . . . . . . . . . . . . . . . . . 20 Typical System Diagram (PC Card Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical System Diagram (Philips MIPS PR31500/PR31700 Bus). . . . . . . . . . . . . 21 Typical System Diagram (Toshiba MIPS TX39xx Bus) . . . . . . . . . . . . . . . . . . 21 Pinout Diagram 144-Pin QFP20 Surface Mount Packages. . . . . . . . . . . . . . . . . 22 Pinout Diagram 220-Pin PFBGA Surface Mount Package. . . . . . . . . . . . . . . . . 23 External Circuitry for CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Generic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MIPS/ISA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Motorola MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 50 Motorola MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 52 Motorola PowerPC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PC Card Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Philips Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Toshiba Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LCD Panel Power-off/Power-on Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power Save Status Bits and Local Bus Memory Access Relative to Power Save Mode. . 63 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 65 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 67 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . 70 Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 71 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . 72 Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 73 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 14 Epson Research and Development Vancouver Design Center Figure 6-25: Figure 6-26: Figure 6-27: Figure 6-28: Figure 6-29: Figure 6-30: Figure 6-31: Figure 6-32: Figure 6-33: Figure 6-34: Figure 6-35: Figure 6-36: Figure 6-37: Figure 6-38: Figure 6-39: Figure 6-40: Figure 7-1: Figure 7-2: Figure 8-1: Figure 10-1: Figure 11-1: Figure 11-2: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 14-1: Figure 14-2: Figure 14-3: Figure 15-1: Figure 20-1: Figure 20-2: Single Color 16-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . 77 Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TFT/D-TFD A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CRT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NTSC Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PAL Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Horizontal Timing for NTSC/PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Vertical Timing for NTSC/PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 MediaPlug A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock Overview Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 MediaPlug Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Display Buffer Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 4/8/16 Bit-per-pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . 159 Image Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4 Bit-Per-Pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 161 8 Bit-Per-Pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 162 4 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 163 8 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 164 NTSC/PAL SVideo-Y (Luminance) Output Levels . . . . . . . . . . . . . . . . . . . 167 NTSC/PAL SVideo-C (Chrominance) Output Levels . . . . . . . . . . . . . . . . . . 168 NTSC/PAL Composite Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 169 NTSC/PAL Image Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Typical Display Dimensions and Visible Display Dimensions for NTSC and PAL . . . 172 Ink/Cursor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Unclipped Cursor Positioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Clipped Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Relationship Between Screen Image and 90 Rotated Image in the Display Buffer . . . 178 Mechanical Drawing 144-pin QFP20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Mechanical Drawing 220-pin PFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . 205 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 15 1 Introduction 1.1 Scope This User Guide provides technical information for the S1D13806 Embedded Memory Display Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This guide is updated as appropriate. Please check the Epson Electronics America Website at www.eea.epson.com or the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13806 is a highly integrated color LCD/CRT/TV graphics controller with embedded memory supporting a wide range of CPUs and display devices. The S1D13806 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PC's, and Office Automation. The S1D13806 supports multiple CPUs, all LCD panel types, CRT, TV, and additionally provides a number of differentiating features. EPSON Independent Simultaneous Display technology allows the user to configure two different images on two different displays, while the SwivelViewTM, Hardware Cursor, Ink Layer, and BitBLT features offer substantial performance benefits. Products requiring digital camera input can take advantage of the directly supported WINNOV Videum(R) Cam digital interface. While focusing on devices targeted by the Microsoft Windows CE Operating System, the S1D13806's impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 16 Epson Research and Development Vancouver Design Center 2 Features Table 2-1 : S1D13806 Features S1D13806 Features Embedded Memory 1280K byte embedded synchronous DRAM. Up to 50MHz data rate (100M Bytes/second). Display buffer address space is directly and contiguously available through the 21-bit address bus. CPU Interfaces Epson E0C33. Hitachi SH-4. Hitachi SH-3. MIPS/ISA. Motorola MC68000. Motorola MC68030. Motorola PowerPC MPC82x. MPU bus interface with programmable READY. NEC MIPS VR41xx. PC Card (PCMCIA). Philips MIPS PR31500/PR31700. StrongARM (PC Card). Toshiba MIPS TX39xx. One-stage write buffer for minimum wait-state CPU writes. Registers are memory-mapped - M/R# pin selects between display buffer and register address space. Display Support 4/8-bit monochrome or 4/8/16-bit color LCD interface for single-panel, single-drive displays. 8-bit monochrome or 8/16-bit color LCD interface for dual-panel, dual-drive displays. Direct support for 9-bit, 12-bit, 18-bit, 2x9-bit, 2x12-bit TFT/D-TFD. Direct support for CRT. Direct support for S-Video/Composite TV output (NTSC or PAL format). Display Modes 4/8/16 bit-per-pixel (bpp) color depths. Up to 64K colors on TFT,CRT and TV. Up to 64K colors in 16 bpp mode on color passive LCD panels using dithering (4096 colors in 4/8 bpp). Up to 64 shades of gray on monochrome passive panels using Frame Rate Modulation (FRM) and Dithering. 4/8 bit-per-pixel color depths are mapped using three 256x4 Look-Up Tables (LUT). Separate LUTs for LCD and CRT/TV. 16 bit-per-pixel modes are mapped directly bypassing the LUT. Display Features SwivelViewTM: 90, 180, 270 hardware rotation of display image. EPSON Independent Simultaneous Display (EISD): displays independent images on different displays (CRT or TV and passive or TFT panel). Virtual Display Support: displays images larger than the physical display size through the use of panning and scrolling. 2D BitBLT Engine. Hardware Cursor/Ink Layer: separate 64x64x2 hardware cursor or 2-bit ink layer for both LCD and CRT/TV. Double Buffering/Multi-pages: for smooth animation and instantaneous screen update. Miscellaneous Power save mode is initiated by software. Built-in MediaPlug Interface for Winnov Camera. Highly Flexible Clocking. Eight configuration pins (CONF[7:0]) are used to configure the chip at power-on. 13 General Purpose Input/Output pins. Operating voltage from 3.0 volts to 3.6 volts. 144-pin QFP20 package. 220-pin PFBGA package S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 17 3 Typical System Implementation Diagrams For pin mapping of each system implementation, see Table 4-10, "CPU Interface Pin Mapping," on pag e34. . Oscillator Oscillator Oscillator Generic BUS VDD CLKI CLKI2 BS# A0 CLKI3 FPDAT[7:4] FPSHIFT FPFRAME FPLINE DRDY A[27:21] CSn# A[20:1] D[15:0] WE0# WE1# RD# WAIT# BCLK RESET# Decoder M/R# CS# AB[20:1] DB[15:0] WE0# WE1# RD# RD/WR# WAIT# BUSCLK RESET# 4-bit Single FPSHIFT LCD Display D[3:0] FPFRAME FPLINE MOD Bias Power S1D13806 GPIOx RED,GREEN,BLUE HRTC VRTC IREF RED,GREEN,BLUE HRTC VRTC CRT IREF Figure 3-1: Typical System Diagram (Generic Bus) . Oscillator Oscillator Oscillator SH-4 BUS CLKI CLKI2 CLKI3 VDD A0 A[21] CSn# A[20:1] D[15:0] WE1# BS# RD/WR# RD# WE0# RDY# CKIO RESET# M/R# CS# AB[20:1] DB[15:0] WE1# BS# RD/WR# RD# WE0# WAIT# FPDAT[7:0] FPSHIFT FPFRAME FPLINE DRDY D[7:0] FPSHIFT 8-bit Single LCD Display Bias Power FPFRAME FPLINE MOD S1D13806 GPIOx GREEN Composite Video Composite TV IREF BUSCLK RESET# IREF Figure 3-2: Typical System Diagram (Hitachi SH-4 Bus) Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 18 Epson Research and Development Vancouver Design Center . Oscillator Oscillator Oscillator SH-3 BUS VDD CLKI2 A0 A[21] CSn# A[20:1] D[15:0] M/R# CS# AB[20:1] DB[15:0] FPFRAME FPLINE WE1# BS# RD/WR# RD# WE0# WAIT# WE1# BS# RD/WR# RD# WE0# WAIT# RED,GREEN,BLUE HRTC VRTC CKIO RESET# BUSCLK RESET# IREF RED,GREEN,BLUE HRTC VRTC DRDY FPFRAME FPLINE MOD Bias Power CLKI3 CLKI FPDAT[7:4] FPDAT[3:0] FPSHIFT 8-bit Dual FPSHIFT LCD Display UD[3:0] LD[3:0] S1D13806 GPIOx CRT IREF Figure 3-3: Typical System Diagram (Hitachi SH-3 Bus) . Oscillator Oscillator Oscillator MC68000 BUS CLKI2 A[23:21] FC0, FC1 Decoder M/R# CLKI3 CLKI FPDAT[8:0] Decoder A[20:1] D[15:0] CS# AB[20:1] DB[15:0] FPLINE FPSHIFT D[8:0] FPSHIFT 9-bit TFT Display FPLINE MOD LDS# UDS# AS# R/W# DTACK# AB0 WE1# BS# RD/WR# WAIT# S1D13806 DRDY GPIOx RED BLUE Luminance Chrominance BCLK RESET# BUSCLK RESET# IREF S-Video TV IREF Figure 3-4: Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Bias Power FPFRAME FPFRAME Epson Research and Development Vancouver Design Center Page 19 . Oscillator Oscillator Oscillator MC68030 BUS CLKI2 A[31:21] FC0, FC1 CLKI3 CLKI Decoder M/R# FPDAT[15:0] Decoder A[20:0] D[31:16] CS# AB[20:0] DB[15:0] FPLINE DS# AS# R/W# SIZ1 SIZ0 DSACK1# WE1# BS# RD/WR# RD# WE0# WAIT# RED,GREEN,BLUE HRTC VRTC BCLK RESET# BUSCLK RESET# IREF DRDY FPSHIFT 16-bit Single D[15:0] LCD FPSHIFT Panel Bias Power FPFRAME FPLINE MOD FPFRAME S1D13806 GPIOx RED,GREEN,BLUE HRTC VRTC CRT IREF Figure 3-5: Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030) . Oscillator Oscillator Oscillator PowerPC BUS CLKI2 A[0:10] CLKI3 CLKI Decoder M/R# FPDAT[11:0] FPSHIFT D[11:0] FPSHIFT Decoder A[11:31] D[0:15] CS# AB[20:0] DB[15:0] 12-bit TFT Display Bias Power FPFRAME FPLINE FPFRAME FPLINE MOD BI# TS# RD/WR# TSIZ0 TSIZ1 TA# WE1# BS# RD/WR# RD# WE0# WAIT# DRDY S1D13806 GPIOx RED,GREEN,BLUE Composite Video CLKOUT RESET# Composite TV IREF BUSCLK RESET# IREF Figure 3-6: Typical System Diagram (Motorola Power PC Bus) Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 20 Epson Research and Development Vancouver Design Center . Oscillator Oscillator Oscillator MIPS BUS CLKI2 BS# RD/WR# A[25:21] Decoder M/R# CLKI3 CLKI VDD FPDAT[15:8] FPDAT[7:0] FPSHIFT UD[7:0] LD[7:0] FPSHIFT 16-bit Dual LCD Panel Bias Power CSn# A[20:0] D[15:0] CS# AB[20:0] DB[15:0] FPFRAME FPLINE DRDY FPFRAME FPLINE MOD S1D13806 GPIOx RED,GREEN,BLUE HRTC MEMW# SBHE# MEMR# RDY BCLK RESET WE0# WE1# RD# WAIT# BUSCLK RESET# RED,GREEN,BLUE HRTC VRTC VRTC CRT IREF IREF Figure 3-7: Typical System Diagram (NEC MIPS VR41xx Bus) . Oscillator Oscillator Oscillator PC Card BUS VDD CLKI2 CLKI3 CLKI BS# A0 FPDAT[23:0] FPSHIFT A[25:21] Decoder M/R# 2x12-bit TFT Panel FPSHIFT D[23:0] Bias Power FPFRAME FPLINE MOD Decoder A[20:1] D[15:0] WE# CE2# OE# CE1# WAIT# RESET Oscillator CS# AB[20:1] DB[15:0] WE0# WE1# RD# RD/WR# WAIT# RESET# BUSCLK FPFRAME FPLINE S1D13806 DRDY GPIOx RED BLUE Luminance Chrominance S-Video TV IREF IREF Figure 3-8: Typical System Diagram (PC Card Bus) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 21 . Oscillator Oscillator Oscillator CLKI2 A[12:0] D[23:16] D[31:24] ALE /CARDREG /CARDIORD /CARDIOWR /CARDxCSH /CARDxCSL /RD /WE /CARDxWAIT DCLKOUT RESET# M/R# CS# BS# AB[16:13] AB[12:0] DB[15:8] DB[7:0] AB20 AB19 AB18 AB17 WE1# RD/WR# RD# WE0# WAIT# BUSCLK RESET# CLKI3 CLKI PR31500 /PR31700 BUS VDD FPDAT[15:8] FPDAT[7:0] FPSHIFT UD[7:0] LD[7:0] FPSHIFT 16-bit Dual LCD Panel Bias Power FPFRAME FPLINE FPFRAME FPLINE MOD S1D13806 DRDY GPIOx RED,GREEN,BLUE HRTC VRTC RED,GREEN,BLUE HRTC VRTC CRT IREF IREF Figure 3-9: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus) . Oscillator Oscillator Oscillator TX3912 BUS VDD CLKI CLKI2 M/R# CS# BS# AB[16:13] AB[12:0] DB[15:8] DB[7:0] AB20 AB19 AB18 AB17 WE1# RD/WR# RD# WE0# WAIT# BUSCLK RESET# IREF RED,GREEN,BLUE Composite Video FPLINE DRDY FPLINE MOD Bias Power FPFRAME FPFRAME CLKI3 FPDAT[11:0] FPSHIFT D[11:0] FPSHIFT 12-bit TFT Panel A[12:0] D[23:16] D[31:24] ALE CARDREG* CARDIORD* CARDIOWR* CARDxCSH* CARDxCSL* RD* WE* CARDxWAIT* DCLKOUT PON* S1D13806 GPIOx Composite TV IREF Figure 3-10: Typical System Diagram (Toshiba MIPS TX39xx Bus) Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 22 Epson Research and Development Vancouver Design Center 4 Pins 4.1 Pinout Diagram 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 FPDAT11 VSS FPSHIFT DRDY VSS 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS TESTEN IOVDD 1 CNF2 2 CNF1 CNF0 FPDAT23 FPDAT22 FPDAT21 FPDAT20 FPDAT19 FPDAT18 FPDAT17 FPDAT16 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT10 IOVDD FPDAT9 FPDAT8 COREVDD VSS FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Reserved FPLINE FPFRAME IOVDD 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 IOVDD AVDD AVSS RED IREF AVDD GREEN AVDD BLUE AVSS HRTC VRTC VSS COREVDD IOVDD VMP0 VMP1 VMP2 VMP3 VMP4 VMP5 VMP6 VMP7 DVDD TEST GPIO12 GPIO11 GPIO10 GPIO9 CNF7 CNF6 CNF5 CNF4 CNF3 DVSS COREVDD RD/WR# RESET# VSS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 CLKI GPIO5 CLKI2 GPIO6 CLKI3 GPIO7 BUSCLK VSS DVSS GPIO8 DTESEN DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 WAIT# DVDD IOVDD WE0# WE1# M/R# VSS RD# CS# BS# S1D13806 A13 A20 A19 A18 A16 A17 A14 A12 A11 A10 A15 A9 A7 A3 A0 A6 A5 A4 A2 A1 A8 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 4-1: Pinout Diagram 144-Pin QFP20 Surface Mount Packages S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 23 T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 4-2: Pinout Diagram 220-Pin PFBGA Surface Mount Package Table 4-1: PFBGA 220-pin Mapping T R P N M L K J H G F E D C B A AB NC RESET# WE1# BS# COREVDD AB2 AB6 AB9 NC AB16 AB19 NC CNF2 NC NC NC NC RD/WR# NC M/R# AB1 AB4 NC AB11 AB14 NC AB20 NC NC NC NC DVDD NC NC NC WE0# NC NC AB7 AB12 AB15 AB18 TESTEN CNF1 NC NC DVSS NC NC WAIT# NC VSS RD# AB0 AB5 AB10 AB13 NC IOVDD NC CNF3 CNF6 NC DB12 DB13 DB14 IOVDD NC NC CS# AB3 AB8 AB17 CNF0 NC VSS CNF5 GPIO9 CNF7 CNF4 NC NC TEST GPIO11 GPIO10 GPIO12 NC VMP6 DVDD VMP7 VMP5 VMP3 NC VMP4 VMP2 VMP0 COREVDD IOVDD VMP1 NC NC HRTC VRTC VSS RED AVDD BLUE AVSS NC NC DB10 DB11 NC DB15 DB6 DB7 DB8 NC DB9 DB2 DB4 DB5 DB3 DB1 DTESTEN NC DB0 GPIO8 VSS BUSCLK DVSS NC CLKI3 CLKI2 GPIO6 GPIO7 NC NC GPIO2 CLKI GPIO5 GPIO3 VSS NC Reserved FPDAT2 FPDAT8 NC GPIO4 GPIO1 NC IOVDD NC FPDAT5 VSS GPIO0 NC NC FPLINE DRDY FPDAT0 FPDAT3 FPDAT6 FPDAT9 NC NC NC NC NC NC FPSHIFT FPDAT1 FPDAT4 NC NC FPFRAME NC VSS NC NC PFDAT7 COREVDD NC IOVDD FPDAT12 FPDAT10 FPDAT16 FPDAT15 FPDAT21 NC IOVDD AVDD GREEN NC NC VSS NC NC AVSS IREF FPDAT11 FPDAT13 FPDAT14 VSS FPDAT20 FPDAT17 FPDAT18 FPDAT22 FPDAT19 NC NC AVDD NC NC NC NC FPDAT23 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note NC is no connection. Reserved must be left unconnected and floating. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 24 Epson Research and Development Vancouver Design Center 4.2 Pin Description Key: Hi-Z I O IO A P C CD CS COx TSx TSxU TSxD = = = = = = = = = = = = = High impedance Input Output Bi-Directional (Input/Output) Analog Power pin CMOS level input CMOS level input with pull down resistor (typical value of 50 at 3.3V) CMOS level Schmitt input CMOS output driver, x denotes driver type (1=2/-2mA, 2=6/-6mA @ 3.3V) Tri-state CMOS output driver, x denotes driver type (1=2/-2mA, 2=6/-6mA @ 3.3V) Tri-state CMOS output driver with pull up resistor (typical value of 100 at 3.3V), x denotes driver type (1=2/-2mA, 2=6/-6mA @ 3.3V) Tri-state CMOS output driver with pull down resistor (typical value of 100 at 3.3V), x denotes driver type (1=2/-2mA, 2=6/-6mA @ 3.3V) 4.2.1 Host Interface Table 4-2 : Host Interface Pin Descriptions Pin Name Type QFP Pin # PFBGA Pin # Cell RESET# State Description * For Generic Bus, this pin must be connected to VSS or IO VDD. * For SH-4/SH-3 Bus, this pin must be connected to VSS or IO VDD. * For MC68K Bus 1, this pin inputs the lower data strobe (LDS#). * For MC68K Bus 2, this pin inputs system address bit 0 (A0) . * For MIPS/ISA Bus, this pin inputs system address bit 0 (SA0). * For PC Card (PCMCIA) Bus, this pin must be connected to VSS or IO VDD. * For Philips PR31500/31700 Bus, this pin inputs system address bit 0 (A0). * For Toshiba TX3912 Bus, this pin inputs system address bit 0 (A0). * For PowerPC Bus, this pin inputs system address bit 31 (A31). SeeTable 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. H3, H2, H4, H1, H5, J3, J1, J4, K2, J5, K1, L2 * For PowerPC Bus, these pins input the system address bits 19 through 30 (A[19:30]). * For all other busses, these pins input the system address bits 12 through 1 (A[12:1]). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. AB0 I 26 K4 CS Hi-Z AB[12:1] I 14-25 C Hi-Z S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 25 Table 4-2 : Host Interface Pin Descriptions (Continued) Pin Name Type QFP Pin # PFBGA Pin # Cell RESET# State Description * For Philips PR31500/31700 Bus, these pins are connected to V DD. * For Toshiba TX3912 Bus, these pins are connected to V DD. * For PowerPC Bus, these pins input the system address bits 15 through 18 (A[15:18]). * For all other busses, these pins input the system address bits 16 through 13 (A[16:13]). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin inputs the IO write command (/CARDIOWR). * For Toshiba TX3912 Bus, this pin inputs the IO write command (CARDIOWR*). * For PowerPC Bus, this pin inputs the system address bit 14 (A14). * For all other busses, this pin inputs the system address bit 17 (A17). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin inputs the IO read command (/CARDIORD). * For Toshiba TX3912 Bus, this pin inputs the IO read command (CARDIORD*). * For PowerPC Bus, this pin inputs the system address bit 13 (A13). * For all other busses, this pin inputs the system address bit 18 (A18). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin inputs the card control register access (/CARDREG). * For Toshiba TX3912 Bus, this pin inputs the card control register access (CARDREG*). * For PowerPC Bus, this pin inputs the system address bit 12 (A12). * For all other busses, this pin inputs the system address bit 19 (A19). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. * For the MIPS/ISA Bus, this pin inputs system address bit 20. Note that for the ISA Bus, the unlatched LA20 must first be latched before input to AB20. * For Philips PR31500/31700 Bus, this pin inputs the address latch enable (ALE). * For Toshiba TX3912 Bus, this pin inputs the address latch enable (ALE). * For PowerPC Bus, this pin inputs the system address bit 11 (A11). * For all other busses, this pin inputs the system address bit 20 (A20). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. AB[16:13] I 10-13 F1, G3, G2, G4 C Hi-Z AB17 I 9 G5 C Hi-Z AB18 I 8 F3 C Hi-Z AB19 I 7 E1 C Hi-Z AB20 I 6 E2 C Hi-Z Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 26 Epson Research and Development Vancouver Design Center Table 4-2 : Host Interface Pin Descriptions (Continued) Pin Name Type QFP Pin # PFBGA Pin # Cell RESET# State Description These pins are the system data bus. * For SH-3/SH-4 Bus, these pins are connected to D[15:0]. * For MC68K Bus 1, these pins are connected to D[15:0]. * For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340). * For Generic Bus, these pins are connected to D[15:0]. * For MIPS/ISA Bus, these pins are connected to SD[15:0]. * For Philips PR31500/31700 Bus, pins DB[15:8] are connected to D[23:16] and pins DB[7:0] are connected to D[31:24]. * For Toshiba TX3912 Bus, pins DB[15:8] are connected to D[23:16] and pins DB[7:0] are connected to D[31:24]. * For PowerPC Bus, these pins are connected to D[0:15]. * For PC Card (PCMCIA) Bus, these pins are connected to D[15:0]. See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the write enable signal for the upper data byte (WE1#). * For MC68K Bus 1, this pin inputs the upper data strobe (UDS#). * For MC68K Bus 2, this pin inputs the data strobe (DS#). * For Generic Bus, this pin inputs the write enable signal for the upper data byte (WE1#). * For MIPS/ISA Bus, this pin inputs the system byte high enable signal (SBHE#). * For Philips PR31500/31700 Bus, this pin inputs the odd byte access enable signal (/CARDxCSH). * For Toshiba TX3912 Bus, this pin inputs the odd byte access enable signal (CARDxCSH*). * For PowerPC Bus, this pin outputs the burst inhibit signal (BI#). * For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal (CE2#). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin is connected to V DD. * For Toshiba TX3912 Bus, this pin is connected to VDD. * For all other busses, this input pin is used to select between the display buffer and register address spaces of the S1D13806. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping. See Table 4-10, "CPU Interface Pin Mapping," on page 34. * For Philips PR31500/31700 Bus, this pin is connected to V DD. * For Toshiba TX3912 Bus, this pin is connected to VDD. * For all other busses, this is the Chip Select input. See Table 4-10, "CPU Interface Pin Mapping," on page 34. See the respective AC Timing diagram for detailed functionality. DB[15:0] IO 40-55 M6, P5, R5, T5, P6, R6, M7, P7, R7, T7, P8, R8, N8, T8, M8, P9 C/TS2 Hi-Z WE1# IO 33 N1 CS/TS2 Hi-Z M/R# I 29 M2 C Hi-Z CS# I 28 K5 C Hi-Z S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 27 Table 4-2 : Host Interface Pin Descriptions (Continued) Pin Name Type QFP Pin # PFBGA Pin # Cell RESET# State Description This pin inputs the system bus clock. It is possible to apply a 2x clock and divide it by 2 internally - see CONF5 in Summary of Configuration Options. * For SH-3/SH-4 Bus, this pin is connected to CKIO. * For MC68K Bus 1, this pin is connected to CLK. * For MC68K Bus 2, this pin is connected to CLK. * For Generic Bus, this pin is connected to BCLK. * For MIPS/ISA Bus, this pin is connected to CLK. * For Philips PR31500/31700 Bus, this pin is connected to DCLKOUT. * For Toshiba TX3912 Bus, this pin is connected to DCLKOUT. * For PowerPC Bus, this pin is connected to CLKOUT. * For PC Card (PCMCIA) Bus, this pin is connected to an external input clock source. See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the bus start signal (BS#). * For MC68K Bus 1, this pin inputs the address strobe (AS#). * For MC68K Bus 2, this pin inputs the address strobe (AS#). * For Generic Bus, this pin is connected to VDD. * For MIPS/ISA Bus, this pin is connected to VDD. * For Philips PR31500/31700 Bus, this pin is connected to V DD. * For Toshiba TX3912 Bus, this pin is connected to V DD. * For PowerPC Bus, this pin inputs the Transfer Start signal (TS#). * For PC Card (PCMCIA) Bus, this pin is connected to V DD. See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13806 needs this signal for early decode of the bus cycle. * For MC68K Bus 1, this pin inputs the read write signal (R/W#). * For MC68K Bus 2, this pin inputs the read write signal (R/W#). * For Generic Bus, this pin inputs the read command for the upper data byte (RD1#). * For MIPS/ISA Bus, this pin is connected to VDD. * For Philips PR31500/31700 Bus, this pin inputs the even byte access enable signal (/CARDxCSL). * For Toshiba TX3912 Bus, this pin inputs the even byte access enable signal (CARDxCSL*). * For PowerPC Bus, this pin inputs the read write signal (RD/WR#). * For PC Card (PCMCIA) Bus, this pin inputs the card enable 1 signal (CE1#). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. BUSCLK I 60 T10 C Hi-Z BS# I 30 M1 CS Hi-Z RD/WR# I 34 P2 CS Hi-Z Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 28 Epson Research and Development Vancouver Design Center Table 4-2 : Host Interface Pin Descriptions (Continued) Pin Name Type QFP Pin # PFBGA Pin # Cell RESET# State This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the read signal (RD#). * For MC68K Bus 1, this pin is connected to VDD. * For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1). * For Generic Bus, this pin inputs the read command for the lower data byte (RD0#). * For MIPS/ISA Bus, this pin inputs the memory read signal (MEMR#). * For Philips PR31500/31700 Bus, this pin inputs the memory read command (/RD). * For Toshiba TX3912 Bus, this pin inputs the memory read command (RD*). * For PowerPC Bus, this pin inputs the transfer size 0 signal (TSIZ0). * For PC Card (PCMCIA) Bus, this pin inputs the output enable signal (OE#). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the write enable signal for the lower data byte (WE0#). * For MC68K Bus 1, this pin must be connected to V DD * For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0). * For Generic Bus, this pin inputs the write enable signal for the lower data byte (WE0#). * For MIPS/ISA Bus, this pin inputs the memory write signal (MEMW#). * For Philips PR31500/31700 Bus, this pin inputs the memory write command (/WE). * For Toshiba TX391 Bus, this pin inputs the memory write command (WE*). * For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1). * For PC Card (PCMCIA) Bus, this pin inputs the write enable signal (WE#). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. Active low input that clears all internal registers and forces all outputs to their inactive states. Note that active high RESET signals must be inverted before input to this pin. * For Toshiba TX3912 Bus, this pin is called NOP*. Description RD# I 31 L4 CS Hi-Z WE0# I 32 M3 CS Hi-Z RESET# I 35 P1 CS 0 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 29 Table 4-2 : Host Interface Pin Descriptions (Continued) Pin Name Type QFP Pin # PFBGA Pin # Cell RESET# State Description The active polarity of the WAIT# output is configurable; the state of CONF[3:0] on the rising edge of RESET# defines the active polarity of WAIT# for some busses - see "Summary of Configuration Options". * For SH-3 Bus, this pin outputs the wait request signal (WAIT#). * For SH-4 Bus, this pin outputs the ready signal (RDY#). * For MC68K Bus 1, this pin outputs the data transfer acknowledge signal (DTACK#). * For MC68K Bus 2, this pin outputs the data transfer and size acknowledge bit 1 (DSACK1#). * For Generic Bus, this pin outputs the wait signal (WAIT#). * For MIPS/ISA Bus, this pin outputs the IO channel ready signal (IOCHRDY). * For Philips PR31500/31700 Bus, this pin outputs the wait state signal (/CARDxWAIT). * For Toshiba TX3912 Bus, this pin outputs the wait state signal (CARDxWAIT*). * For PowerPC Bus, this pin outputs the transfer acknowledge signal (TA#). * For PC Card (PCMCIA) Bus, this pin outputs the wait signal (WAIT#). See Table 4-10, "CPU Interface Pin Mapping," on page 34 for summary. See the respective AC Timing diagram for detailed functionality. WAIT# IO 39 P4 C/TS2 Hi-Z Note When WAIT# is always driven, WAIT# is in its inactive state at RESET#. CONF[3:0] determines whether WAIT# is active high or low. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 30 Epson Research and Development Vancouver Design Center 4.2.2 LCD Interface Table 4-3 : LCD Interface Pin Descriptions Pin Name Type QFP Pin # PFBGA Pin # C16, D14, F12, E14, D15, E16, E15, G12, G13, F15, G16, H12, G15, H13, H14, J12, J15, J14, K13, K15, K14, K12, L15, L14 P16 N14 M15 Cell RESET# State Description FPDAT[23:0] O 107-100, 91-90, 9893, 87-80 CO2 0 Panel data bus. Not all pins are used for some panels - see Table 4-10, "CPU Interface Pin Mapping," on page 34 for details. Unused pins are driven low. FPFRAME FPLINE FPSHIFT O O O 74 75 78 CO2 CO2 CO2 0 0 0 Frame pulse Line pulse Shift clock This is a multi-purpose pin: * For TFT/D-TFD panels this is the display enable output (DRDY). * For passive LCD with Format 1 interface this is the 2nd Shift Clock (FPSHIFT2). * For all other LCD panels this is the LCD backplane bias signal (MOD). See Table 4-11, "LCD Interface Pin Mapping," on page 35 and REG[030h] for details. DRDY O 77 M14 CO2 0 4.2.3 MediaPlug Interface Table 4-4 : MediaPlug Pin Description Pin Name VMP[7] Type O QFP Pin # 131 PFBGA Pin # E8 Cell CO2 RESET# State 0 MediaPlug VMPLCTL pin. MediaPlug VMPRCTL pin. VMP[6] I 130 B7 CD Hi-Z Internal pull-down resistors (typical value of 50 at 3.3V respectively) pull the reset states to 0. External pull-up resistors can be used to pull the reset states to 1. MediaPlug VMPD[0:3] pins. See Section 17.3, "MediaPlug Interface Pin Mapping" on page 188. Description VMP[5:2] IO 129-126 D8, A8, C8, C/TS2U 0 or Hi-Z Internal pull-up resistors (typical value of 100 at 3.3V respectively) E9 pull the reset states to 1. External pull-down resistors can be used to pull the reset states to 0. A9 D9 CO2 CO2 0 0 MediaPlug VMPCLK pin. MediaPlug VMPCLKN pin. VMP[1] VMP[0] O O 125 124 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 31 Note The RESET# states of VMP[5:2] are 0 if VMP is enabled, otherwise Hi-Z. Note When the MediaPlug interface is enabled, GPIO12 is configured as the MediaPlug output pin VMPEPWR. 4.2.4 CRT Interface Table 4-5 : CRT Interface Pin Descriptions Pin Name HRTC VRTC RED GREEN BLUE IREF Type O O O O O I QFP Pin # 119 120 112 115 117 113 PFBGA Pin # C10 B10 E11 B12 C11 A13 Cell CO2 CO2 A A A A RESET# State 0 0 -- -- -- -- Description Horizontal retrace signal for CRT Vertical retrace signal for CRT Analog output for CRT color Red / S-Video Luminance Analog output for CRT color Green / Composite Video Out Analog output for CRT color Blue / S-Video Chrominance Current reference for DAC. If the DAC is not needed, this pin must be left unconnected and floating. 4.2.5 General Purpose IO Table 4-6 : General Purpose IO Pin Descriptions Pin Name Type QFP Pin # PFBGA Pin # D7 Cell RESET# State Bi-directional GPIO pin. GPIO12 IO 134 C/TS2 1 or Hi-Z When the MediaPlug interface is enabled, GPIO12 is configured as the MediaPlug output pin VMPEPWR. Description GPIO[11:0] IO A6, E7, B5, N9, R11, 135-137, T11, R12, 57, 61, 63, R13, P12, 65, 67-71 M11, P13, T14 C/TS2 Hi-Z Bi-directional GPIO pin. Note The RESET# state of GPIO12 is 1 if MediaPlug is enabled, otherwise Hi-Z. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 32 Epson Research and Development Vancouver Design Center 4.2.6 Configuration Table 4-7 : Configuration Pin Descriptions Pin Name Type QFP Pin # 138-142, 2-4 PFBGA Pin # A5, B4, C5, E6, C4, C1, D3, F5 Cell RESET# State Input Configuration pin. C Hi-Z State of pins are latched at RESET# to configure S1D13806 -- Table 4.3, "Summary of Configuration Options," on page 33 for details. Description CONF[7:0] I 4.2.7 Miscellaneous Table 4-8 : Miscellaneous Interface Pin Descriptions Pin Name CLKI CLKI2 CLKI3 TESTEN DTESEN TEST IOVDD COREVDD AVDD DVDD Type I I I I I -- P P P P QFP Pin # 66 64 62 5 56 133 PFBGA Pin # T12 M10 N10 E3 T9 B6 Cell C C C CD C -- P P P P RESET# State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z -- -- -- -- -- Description Input clock for the internal pixel clock (PCLK), memory clock (MCLK), and MediaPlug clock. Input clock for the internal pixel clock (PCLK) and MediaPlug clock. Input clock for memory clock (MCLK) (Possible to use for PCLK and MediaPlug clock.) Test Enable. This pin should be connected to VSS for normal operation. Test Enable for embedded SDRAM. This pin should be connected to VSS for normal operation. Test Pin. This pin must be left unconnected and floating. VDD for IO (IO VDD) VDD for core (Core VDD) VDD for DAC (DAC VDD). When the DAC is not used this pin must be connected to DVDD. VDD for embedded SDRAM (SDRAM VDD) E4, N5, 1, 37, 73, M13, H16, 92, 109, 123 D12, B9 27, 89, 122 L1, J16, C9 110, 114, 116 38, 132 36, 59, 72, 79, 88, 99, 108, 121, 144 111, 118 58, 143 76 A14, C12, D11 A7, T3 M4, M9, N12, M16, J13, F16, E13, A10, D5 B13, B11 A3, R10 L12 VSS P P -- VSS AVSS DVSS Reserved P P -- P P -- -- -- -- VSS for DAC (DAC VSS) VSS for embedded SDRAM (SDRAM VSS) This pin must be left unconnected and floating. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 33 4.3 Summary of Configuration Options Table 4-9 : Summary of Power-On/Reset Options Pin Name state of this pin at rising edge of RESET# is used to configure: 1 Select host bus interface as follows: CONF6 CONF3 CONF2 CONF1 CONF0 Host Bus (1/0) 0 CONF6, CONF[3:0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Generic; Little Endian; Active Low WAIT# with tristate note Generic; Little Endian; Active Low WAIT# always driven Generic; Little Endian; Active High WAIT# with tristate note Reserved Generic; Big Endian; Active Low WAIT# with tristate note Generic; Big Endian; Active Low WAIT# always driven Generic; Big Endian; Active High WAIT# with tristate note Reserved MIPS/ISA; Little Endian; Active Low WAIT# with tristate note MIPS/ISA; Little Endian; Active Low WAIT# always driven MIPS/ISA; Little Endian; Active High WAIT# with tristate note Reserved MC68000; Big Endian; Active High WAIT# with tristate note Reserved MC68030; Big Endian; Active High WAIT# with tristate note Reserved PR31500/31700/TX3912; Little Endian; Active Low WAIT# with tristate note PR31500/31700/TX3912; Little Endian; Active Low WAIT# always driven PC Card; Little Endian; Active Low WAIT# with tristate note PC Card; Little Endian; Active Low WAIT# always driven Reserved Reserved MPC821; Big Endian; Active High WAIT# with tristate note Reserved SH3; Little Endian; Active Low WAIT# with tristate note SH3; Little Endian; Active Low WAIT# always driven SH4; Little Endian; Active High WAIT# with tristate note Reserved SH3; Big Endian; Active Low WAIT# with tristate note SH3; Big Endian; Active Low WAIT# always driven SH4; Big Endian; Active High WAIT# with tristate note Reserved CONF4 CONF5 CONF7 Reserved. Must be tied to ground. BUSCLK input divided by 2 BUSCLK input not divided Configures GPIO12 as MediaPlug output pin Configure GPIO12 for normal use and disables MediaPlug VMPEPWR and enables MediaPlug functionality. functionality. Note WAIT# is tristated (high impedance) when the chip is not accessed by the host Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 34 Epson Research and Development Vancouver Design Center 4.4 Multiple Function Pin Mapping Table 4-10 : CPU Interface Pin Mapping S1D13806 Pin Names AB20 AB19 AB18 AB17 AB[16:13] AB[12:1] AB0 DB[15:8] DB[7:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# BCLK Connected to VDD Generic A20 A19 A18 A17 A[16:13] A[12:1] Connected to VDD1 Hitachi SH-4/ SH-3 A20 A19 A18 A17 A[16:13] A[12:1] Connected to VDD1 MIPS/ISA LatchA20 SA19 SA18 SA17 SA[16:13] SA[12:1] SA0 SD[15:0] SD[7:0] SBHE# Motorola Motorola MC68K MC68K Bus 2 Bus 1 A20 A19 A18 A17 A[16:13] A[12:1] LDS# D[15:8] D[7:0] UDS# A20 A19 A18 A17 A[16:13] A[12:1] A0 D[31:24] D[23:16] DS# Motorola PowerPC A11 A12 A13 A14 A[15:18] A[19:30] A31 D[0:7] D[8:15] BI# PC Card A20 A19 A18 A17 A[16:13] A[12:1] Connected to VDD1 Philips PR31500 /PR31700 ALE /CARDREG /CARDIORD /CARDIOWR A[12:1] A0 D[23:16] D[31:24] /CARDxCSH Toshiba TX3912 ALE CARDREG* CARDIORD* CARDIOWR* A[12:1] A0 D[23:16] D[31:24] CARDxCSH* Connected to VDD D[15:0] D[7:0] WE1# D[15:8] D[7:0] WE1# D[15:0] D[7:0] CE2# External Decode External Decode CKIO BS# RD/WR# RD# WE0# WAIT# RESET# CLK Connected to VDD Connected to VDD Connected to VDD Connected to VDD CLK AS# CLKOUT TS# RD/WR# TSIZ0 TSIZ1 TA# RESET# External Oscillator2 Connected to VDD CLK AS# R/W# Connected to VDD Connected to VDD DCLKOUT DCLKOUT Connected to VDD /CARDxCSL /RD /WE CARDxCSL* RD* WE* RD1# RD0# WE0# WAIT# RESET# R/W# SIZ1 SIZ0 CE1# OE# WE# WAIT# inverted RESET MEMR# MEMW# IOCHRDY DTACK# DSACK1# inverted RESET RESET# RESET# /CARDxWAIT CARDxWAIT* RESET# PON* Note All GPIO pins default to input on reset and unless programmed otherwise, must be connected to either VSS or IO VDD if not used. Note 1 AB0 is not used internally for these busses and must be connected to either VSS or IO VDD. For further information on interfacing the S1D13806 to the PC Card bus, see Interfacing to the PC Card Bus, document number X28B-G-005-xx. 2 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 35 4.5 LCD Interface Pin Mapping Table 4-11 : LCD Interface Pin Mapping S1D13806 Pin Names FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT16 FPDAT17 FPDAT18 FPDAT19 FPDAT20 FPDAT21 FPDAT22 FPDAT23 driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 MOD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 driven 0 driven 0 driven 0 driven 0 D0 (R2)1 D1 (B1)1 D2 (G1)1 D3 (R1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPSHIFT2 D0 (B5) 1 Monochrome Passive Panel Single 4-bit 8-bit Dual 8-bit Single 4-bit Color Passive Panel Single Single Format 1 Format 2 8-bit 8-bit Color Active (TFT) Panel Single 16-Bit FPLINE FPSHIFT MOD D0 (G3) 1 Dual 8-bit 16-bit 9-bit 12-bit 18-bit 2x9-bit 2x12-bit FPFRAME DRDY R2 R1 R0 G2 G1 G0 B2 B1 B0 driven 0 R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 G2 G1 G0 B2 B1 B0 R0 R02 R01 R00 G02 G01 G00 B02 B01 B00 driven 0 R12 driven 0 G12 G11 driven 0 B12 B11 R11 R10 driven 0 G10 driven 0 B10 driven 0 R03 R02 R01 G03 G02 G01 B03 B02 B01 R00 R13 G00 G13 G12 B00 B13 B12 R12 R11 R10 G11 G10 B11 B10 D0 (R6) 1 LD0 LD0 (241-R2)1 (241-G3)1 LD1 (241-B1)1 LD2 (241-G1)1 LD1 (241-R3)1 LD2 (241-B2)1 D1 (R5)1 D2 (G4)1 D3 (B3)1 D4 (R3)1 D5 (G2)1 D6 (B1)1 D7 (R1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 D1 (R3)1 D2 (B2)1 D3 (G2)1 D4 (R2)1 D5 (B1)1 D6 (G1)1 D7 (R1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 D1 (G5)1 D2 (B4)1 D3 (R4)1 D8 (B5)1 D9 (R5)1 D10 (G4)1 D11 (B3)1 D4 (G3)1 D5 (B2)1 D6 (R2)1 D7 (G1)1 D12 (R3)1 D13 (G2)1 D14 (B1)1 D15 (R1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 LD3 LD3 (241-R1)1 (241-G2)1 UD0 (1-R2)1 UD1 (1-B1)1 UD2 (1-G1)1 UD3 (1-R1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 UD0 (1-G3)1 UD1 (1-R3)1 UD2 (1-B2)1 UD3 (1-G2)1 LD4 (241-R2)1 LD5 (241-B1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 LD6 driven 0 driven 0 (241-G1)1 LD7 driven 0 (241-R1)1 UD4 (1-R2)1 UD5 (1-B1)1 UD6 (1-G1)1 UD7 (1-R1)1 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 G0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 Note pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers. The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see Section 6.5, "Display Interface" on page 64. 1These Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 36 Epson Research and Development Vancouver Design Center 4.6 CRT/TV Interface The following figure shows external circuitry for the CRT/TV interface. CRT/TV (REG[05Bh] bit 3 = 0) DAC VDD = 3.3V CRT Only (REG[05Bh] bit 3 =1) OR DAC VDD = 3.3V CRT Only (REG[05Bh] bit 3 =1) OR DAC VDD = 2.7V to 5.5V IREF 9.2 mA or 4.6 mA 1.5k 1% 9.2 mA 4.6 mA 1.5k 1% 4.6 mA 1F V+ R LM334 V- 2N2222 2N2222 1k 1% DAC VSS 69.8 1% DAC VSS 140 1% DAC VSS 1k 1% DAC VSS 290 1% 29 1% 1N457 DAC VSS DAC VSS R G B 150 1% 150 1% 150 1% } DAC VSS DAC VSS DAC VSS To CRT/TV Figure 4-3: External Circuitry for CRT Interface Note Example implementation only, individual characteristics of components may affect actual IREF current. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 37 5 D.C. Characteristics Table 5-1 : Absolute Maximum Ratings Symbol IO VDD Core VDD DAC VDD SDRAM VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time VSS - 0.3 to 4.0 VSS - 0.3 to 4.0 VSS - 0.3 to 4.0 VSS - 0.3 to 4.0 VSS - 0.3 to VDD + 0.5 VSS - 0.3 to VDD + 0.5 -65 to 150 260 for 10 sec. max at lead Rating V V V V V V C C Units Table 5-2 : Recommended Operating Conditions Symbol IO VDD Core VDD DAC VDD SDRAM VDD VIN TOPR Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage Operating Temperature Condition VSS = 0 V VSS = 0 V VSS = 0 V VSS = 0 V 3.0 3.0 3.0 3.0 VSS -40 25 Min 3.3 3.3 3.3 3.3 Typ 3.6 3.6 3.6 3.6 VDD 85 Max V V V V V C Units Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 38 Epson Research and Development Vancouver Design Center Table 5-3 : Electrical Characteristics for VDD = 3.3V typical Symbol IDDS IIZ IOZ VOH Parameter Quiescent Current Input Leakage Current Output Leakage Current High Level Output Voltage Condition Quiescent Conditions -- -- VDD = min IOH = -2mA (Type1), -6mA (Type2) VDD = min IOL = 2mA (Type1), 6mA (Type2) LVTTL level, VDD = max LVTTL level, VDD = min LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt VI = VDD VI = 0V Type 1 Type 2 Type 1 Type 2 1.1 0.6 0.1 20 40 20 40 50 100 50 100 120 240 120 240 10 10 10 2.0 0.8 2.4 1.8 -1 -1 VDD - 0.3 Min Typ 1 1 Max 170 Units uA A A V VOL VIH VIL VT+ VTVH1 RPD RPU CI CO CIO Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Hysteresis Voltage Pull-Down Resistance Pull-Up Resistance Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance 0.3 V V V V V V k k k k pF pF pF S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 39 6 A.C. Characteristics Conditions: VDD = 3.3V 10% (IO and Core) TA = -40 C to 85 C Trise and Tfall for all inputs must be < 5 ns (10% ~ 90%) CL = 50pF (CPU Interface), unless noted CL = 100pF (LCD Panel Interface) CL = 10pF (Display Memory Interface) CL = 10pF (CRT Interface) 6.1 Clock Timing t PWH t PWL 90% V IH VIL 10% tr t T OSC f Figure 6-1: Clock Input Requirement Table 6-1 : Clock Input Requirements for BUSCLK, CLKI, CLKI2, and CLKI3 When Not Divided Symbol fOSC TOSC tPWH tPWL tf tr Input Clock Frequency Input Clock Period Input Clock Pulse Width High Input Clock Pulse Width Low Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 1/fOSC 6 6 5 5 Parameter Min Max Note Units MHz ns ns ns ns ns Note For maximum internal clock frequency values see Table 6-4:, "Internal Clock Requirements," on page 41. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 40 Epson Research and Development Vancouver Design Center Table 6-2 : Clock Input Requirements for MCLK Source when Source Divided Symbol fOSC TOSC tPWH tPWL tf tr Input Clock Frequency Input Clock Period Input Clock Pulse Width High Input Clock Pulse Width Low Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 1/fOSC 5.6 5.6 5 5 Parameter Min Max 80 Units MHz ns ns ns ns ns Note For MCLK source selection see Section 7.3, "Clock Selection" on page 94. Note For maximum internal clock frequency values see Table 6-4:, "Internal Clock Requirements," on page 41. Table 6-3 : Clock Input Requirements for LCD PCLK, CRT/TV PCLK, or MediaPlug Source when Source Divided Symbol fOSC TOSC tPWH tPWL tf tr Input Clock Frequency Input Clock Period Input Clock Pulse Width High Input Clock Pulse Width Low Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 1/fOSC 4.5 4.5 5 5 Parameter Min Max 100 Units MHz ns ns ns ns ns Note For PCLK source selection see Section 7.3, "Clock Selection" on page 94. Note For maximum internal clock frequency values see Table 6-4:, "Internal Clock Requirements," on page 41. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 41 6.2 Internal Clocks This section provides the minimum and maximum required frequencies of the internal clocks used by the S1D13806. For detailed information on the internal clocks, refer to Section 7, "Clocks" on page 92. Table 6-4: Internal Clock Requirements Symbol fMCLK fLCD PCLK fCRT/TV PCLK fMediaPlug Clock fBCLK Parameter Memory Clock Frequency LCD Pixel Clock Frequency CRT/TV Pixel Clock Frequency MediaPlug Clock Frequency Internal Bus Clock Frequency Min 5 Max 50 Note 1 Note 2 20 Note 3 Units MHz MHz MHz MHz MHz Note 1. The maximum LCD pixel clock for TFT panels is 65MHz. The maximum LCD pixel clock for passive panels is 40MHz. 2. The maximum CRT pixel clock is 65MHz. The TV pixel clock for NTSC output is fixed at 14.318MHz. The TV pixel clock for PAL output is fixed at 17.734MHz. 3. For maximum BCLK frequencies refer to the specific CPU Interface Timing in Section 6.3, "CPU Interface Timing" on page 42. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 42 Epson Research and Development Vancouver Design Center 6.3 CPU Interface Timing 6.3.1 Generic Interface Timing TCLK CLK t2 t3 t4 A[20:1] M/R# t5 t6 CS# RD0#, RD1#1 WE0#, WE1# t7 WAIT# t9 D[15:0](write) t11 D[15:0](read) t12 t13 t10 t8 Figure 6-2: Generic Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note WAIT# is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 43 Table 6-5 : Generic Interface Timing Symbol fCLK TCLK t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Clock Frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#, RD1# = 0 or WE0#, WE1# = 0 A[20:1], M/R# hold from rising edge of either RD0#, RD1# or WE0#, WE1# CS# hold from rising edge of either RD0#, RD1# or WE0#, WE1# Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# tristate D[15:0] setup to third CLK where CS# = 0 and WE0#, WE1# = 0 (write cycle) D[15:0] hold (write cycle) Falling edge RD0#, RD1# to D[15:0] driven (read cycle) D[15:0] setup to rising edge WAIT# (read cycle) Rising edge of RD0#, RD1# to D[15:0] tri-state (read cycle) 1/fCLK 6 6 4 0 0 5 4 0 0 3 0 3 10 15 13 Parameter Min Max 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 44 Epson Research and Development Vancouver Design Center 6.3.2 Hitachi SH-4 Interface Timing TCKIO CKIO t4 A[20:1], M/R# RD/WR# t6 BS# t8 CSn# t9 WEn# RD# t11 RDY# t13 D[15:0](write) t15 D[15:0](read) t16 t14 t12 t18 t10 t12 t7 t17 t5 t2 t3 Figure 6-3: Hitachi SH-4 Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note The SH-4 Wait State Control Register for the area in which the S1D13806 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). Note RDY# is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 45 Table 6-6 : Hitachi SH-4 Interface Timing Symbol fCKIO TCKIO t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 Clock Frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R#, RD/WR# setup to CKIO A[20:1], M/R#, RD/WR# hold from CS# BS# setup BS# hold CSn# setup Falling edge RD# to DB[15:0] driven CKIO to RDY# high Falling edge CSn# to RDY# driven CKIO to RDY# delay DB[15:0] setup to 2 nd Parameter Min1 1/fCKIO 6 6 4 0 4 3 3 3 4 3 4 0 0 0 6 3 3 Max1 66 Units MHz ns ns ns ns ns ns ns ns ns 22 12 13 ns ns ns ns ns ns CKIO after BS# (write cycle) DB[15:0] hold (write cycle) DB[15:0] valid to RDY# falling edge (read cycle) Rising edge RD# to DB[15:0] tri-state (read cycle) CSn# high setup to CKIO Falling edge CKIO to RDY# tri-state 29 15 ns ns ns Note 1. Two software WAIT states are required. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 46 Epson Research and Development Vancouver Design Center 6.3.3 Hitachi SH-3 Interface Timing TCKIO CKIO t4 A[20:1], M/R# RD/WR# t6 BS# t8 CSn# t9 WEn# RD# t11 WAIT# t13 D[15:0](write) t15 D[15:0](read) t16 t14 t12 t10 t12 t17 t7 t5 t2 t3 Figure 6-4: Hitachi SH-3 Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note The SH-3 Wait State Control Register for the area in which the S1D13806 resides must be set to a non-zero value. Note WAIT# is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 47 Table 6-7 : Hitachi SH-3 Interface Timing Symbol fCKIO TCKIO t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Clock Frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R#, RD/WR# setup to CKIO A[20:1], M/R#, RD/WR# hold from CS# BS# setup BS# hold CSn# setup Falling edge RD# to DB[15:0] driven Rising edge CSn# to WAIT# tri-state Falling edge CSn# to WAIT# driven CKIO to WAIT# delay DB[15:0] setup to 2 nd Parameter Min1 1/fCKIO 6 6 4 0 4 3 3 3 4 3 4 0 0 0 6 3 Max1 66 Units MHz ns ns ns ns ns ns ns ns ns 17 16 21 ns ns ns ns ns ns CKIO after BS# (write cycle) DB[15:0] hold (write cycle) DB[15:0] valid to WAIT# rising edge (read cycle) Rising edge RD# to DB[15:0] tri-state (read cycle) CSn# high setup to CKIO 29 ns ns Note 1. Two software WAIT states are required when fCKIO is greater than 33MHz. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 48 Epson Research and Development Vancouver Design Center 6.3.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx) TBUSCLK BUSCLK t2 t3 t4 LatchA20 SA[19:0] M/R#, SBHE# t5 t6 CS# MEMR# MEMW# t7 IOCHRDY t9 SD[15:0](write) t11 SD[15:0](read) t12 t13 t10 t8 Figure 6-5: MIPS/ISA Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note IOCHRDY is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 49 Table 6-8 : MIPS/ISA Interface Timing Symbol fBUSCLK TBUSCLK t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Clock Frequency Clock period Clock pulse width high Clock pulse width low LatchA20, SA[19:0], M/R#, SBHE# setup to first BUSCLK where CS# = 0 and either MEMR# = 0 or MEMW# = 0 LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge of either MEMR# or MEMW# CS# hold from rising edge of either MEMR# or MEMW# Falling edge of either MEMR# or MEMW# to IOCHRDY# driven low Rising edge of either MEMR# or MEMW# to IOCHRDY# tri-state SD[15:0] setup to third BUSCLK where CS# = 0 MEMW# = 0 (write cycle) SD[15:0] hold (write cycle) Falling edge MEMR# toSD[15:0] driven (read cycle) SD[15:0] setup to rising edge IOCHRDY# (read cycle) Rising edge of MEMR# toSD[15:0] tri-state (read cycle) 1/fBUSCLK 6 6 4 0 0 3 2 0 0 4 0 6 29 15 11 Parameter Min Max 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 50 Epson Research and Development Vancouver Design Center 6.3.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000) TCLK CLK t4 A[20:1] M/R# t6 CS# t17 AS# t11 UDS# LDS# t7 R/W# t9 DTACK# t12 D[15:0](write) t14 D[15:0](read) t15 t16 t13 t10 t8 t5 t2 t3 Figure 6-6: Motorola MC68K Bus 1 Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note DTACK# is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 51 Table 6-9 : Motorola MC68K Bus 1 Interface Timing Symbol fCLK TCLK t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Clock Frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 A[20:1], M/R# hold from AS# CS# hold from AS# R/W# setup to before to either UDS#=0 or LDS# = 0 R/W# hold from AS# AS# = 0 and CS# = 0 to DTACK# driven high AS# high to DTACK# high First BCLK where AS# = 1 to DTACK# high impedance D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 (write cycle) D[15:0] hold from falling edge of DTACK# (write cycle) Falling edge of UDS#=0 or LDS# = 0 to DB driven (read cycle) D[15:0] valid to DTACK# falling edge (read cycle) UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle) AS# high setup to CLK 0 0 3 0 6 4 30 1/fCLK 6 6 5 0 0 10 0 1 4 19 16 Parameter Min Max 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 52 Epson Research and Development Vancouver Design Center 6.3.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030) TCLK CLK t4 A[20:0] SIZ[1:0] M/R# t6 CS# t17 AS# t11 DS# t7 R/W# t9 DSACK1# t12 D[31:16](write) t14 D[31:16](read) t15 t16 t13 t10 t8 t5 t2 t3 Figure 6-7: Motorola MC68K Bus 2 Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note DSACK1# is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 53 Table 6-10 : Motorola MC68K Bus 2 Interface Timing Symbol fCLK TCLK t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Clock Frequency Clock period Clock pulse width high Clock pulse width low A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# = 0, and DS#= 0 A[20:0], SIZ[1:0], M/R# hold from AS# CS# hold from AS# R/W# setup to DS# R/W# hold from AS# AS# = 0 and CS# = 0 to DSACK1# driven high AS# high to DSACK1# high First BCLK where AS# = 1 to DSACK1# high impedance D[31:16] valid to third CLK where CS# = 0 AS# = 0, and DS#= 0 (write cycle) D[31:16] hold from falling edge of DSACK1# (write cycle) Falling edge of DS#= 0 to DB driven (read cycle) D[31:16] valid to DSACK1# falling edge (read cycle) DS# high to D[31:16] invalid/high impedance (read cycle) AS# high setup to CLK 1/fCLK 6 6 5 0 0 10 0 1 4 3 0 0 3 0 6 4 30 19 16 Parameter Min Max 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 54 Epson Research and Development Vancouver Design Center 6.3.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) TCLKOUT CLKOUT t4 A[11:31], RD/WR# TSIZ[0:1], M/R# t6 CS# t8 TS# t10 TA# t14 BI# t17 D[0:15](write) t19 D[0:15](read) t20 t21 t18 t15 t16 t11 t12 t13 t9 t7 t5 t2 t3 Figure 6-8: Motorola PowerPC Interface Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). Note TA# is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 55 Table 6-11 : Motorola PowerPC Interface Timing Symbol fCLKOUT TCLKOUT t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 Clock Frequency Clock period Clock pulse width low Clock pulse width high AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup AB[11:31], RD/WR#, TSIZ[0:1], M/R# hold CS# setup CS# hold TS# setup TS# hold CLKOUT to TA# driven CLKOUT to TA# low CLKOUT to TA# high negative edge CLKOUT to TA# tri-state CLKOUT to BI# driven CLKOUT to BI# high negative edge CLKOUT to BI# tri-state DB[15:0] setup to 2nd CLKOUT after TS# = 0 (write cycle) DB[15:0] hold (write cycle) CLKOUT to DB driven (read cycle) DB[15:0] valid to TA# falling edge (read cycle) CLKOUT to DB[15:0] tri-state (read cycle) 1/fCLKOUT 6 6 0 0 1 1 1 1 5 4 5 3 5 4 3 0 0 0 0 3 11 14 15 12 15 14 9 Parameter Min Max 45 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note Output pin loading on DB[15:0], TA#, BI# is 10pF. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 56 Epson Research and Development Vancouver Design Center 6.3.8 PC Card Timing (e.g. StrongARM) TCLK CLK (provided externally) t2 t3 t4 A[20:1] M/R# CE1#, CE2# t5 t6 CS# OE# WE# t7 WAIT# t9 D[15:0](write) t11 D[15:0](read) t12 t13 t10 t8 Figure 6-9: PC Card Timing Note BUSCLK cannot be divided by 2 for this interface. CONF5 must be set to 0 (BUSCLK not divided). S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 57 Table 6-12: PC Card Timing Symbol fCLK TCLK t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either OE# = 0 or WE# = 0 A[20:1], M/R# hold from rising edge of either OE# or WE# CS# hold from rising edge of either OE# or WE# Falling edge of either OE# or WE# to WAIT# driven low Rising edge of either OE# or WE# to WAIT# tri-state D[15:0] setup to third CLK where CE1# = 0, CE2# = 0 and WE# = 0 (write cycle) D[15:0] hold (write cycle) Falling edge OE# to D[15:0] driven (read cycle) D[15:0] setup to rising edge WAIT# (read cycle) Rising edge of OE# to D[15:0] tri-state (read cycle) Min 1/fCLK 6 6 4 0 0 5 3 0 0 9 0 3 Max 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 15 13 10 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 58 Epson Research and Development Vancouver Design Center 6.3.9 Philips Interface Timing (e.g. PR31500/PR31700) TDCLKOUT DCLKOUT t4 ADDR[12:0] t6 ALE t8 /CARDREG t7 t5 t2 t3 /CARDxCSH /CARDxCSL /CARDIORD /CARDIOWR /WE /RD t9 t10 /CARDxWAIT t11 D[31:16](write) t13 D[31:16](read) t14 t15 t12 Figure 6-10: Philips Interface Timing Note /CARDxWAIT is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 59 Table 6-13 : Philips Interface Timing Symbol fDCLKOUT TDCLKOUT t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Clock frequency Clock period Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle ADDR[12:0] hold from command invalid ADDR[12:0] setup to falling edge ALE ADDR[12:0] hold from falling edge ALE /CARDREG hold from command invalid Falling edge of chip select to /CARDxWAIT driven Command invalid to /CARDxWAIT tri-state D[31:16] valid to first CLK of cycle (write cycle) D[31:16] hold from rising edge of /CARDxWAIT Chip select to D[31:16] driven (read cycle) D[31:16] setup to rising edge /CARDxWAIT (read cycle) Command invalid to D[31:16] tri-state (read cycle) 1/fDCLKOUT 6 6 10 0 10 5 0 0 5 10 0 1 0 5 25 ns ns ns 15 25 Parameter Min Max 75 Units MHz ns ns ns ns ns ns ns ns ns ns ns Note If BUSCLK exceeds 37.5MHz, it must be divided by 2 using CONF5 (see Table 4-9, "Summary of Power-On/Reset Options," on page 33). Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 60 Epson Research and Development Vancouver Design Center 6.3.10 Toshiba Interface Timing (e.g. TX39xx) TDCLKOUT DCLKOUT t4 ADDR[12:0] t6 ALE t8 CARDREG* t7 t5 t2 t3 CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* t9 t10 CARDxWAIT* t11 D[31:16](write) t13 D[31:16](read) t14 t15 t12 Figure 6-11: Toshiba Interface Timing Note CARDxWAIT* is always driven when CONF6 =1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 61 Table 6-14 : Toshiba Interface Timing Symbol fDCLKOUT TDCLKOUT t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Clock frequency Clock period Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle ADDR[12:0] hold from command invalid ADDR[12:0] setup to falling edge ALE ADDR[12:0] hold from falling edge ALE CARDREG* hold from command invalid Falling edge of chip select to CARDxWAIT* driven Command invalid to CARDxWAIT* tri-state D[31:16] valid to first CLK of cycle (write cycle) D[31:16] hold from rising edge of CARDxWAIT* Chip select to D[31:16] driven (read cycle) D[31:16] setup to rising edge CARDxWAIT* (read cycle) Command invalid to D[31:16] tri-state (read cycle) 1/fDCLKOUT 6 6 10 0 10 5 0 0 5 10 0 1 0 5 25 ns ns ns 15 25 Parameter Min Max 75 Units MHz ns ns ns ns ns ns ns ns ns ns ns Note If BUSCLK exceeds 37.5MHz, it must be divided by 2 using CONF5 (see Table 4-9, "Summary of Power-On/Reset Options," on page 33). Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 62 Epson Research and Development Vancouver Design Center 6.4 Power Sequencing 6.4.1 LCD Power Sequencing LCD Enable Bit (REG[1FCh] bit 0) FPFRAME FPLINE FPSHIFT FPDATA DRDY t1 t2 Figure 6-12: LCD Panel Power-off/Power-on Timing Table 6-15 : LCD Panel Power-off/Power-on Symbol t1 t2 Parameter LCD Enable Bit low to FPFRAME, FPLINE, FPSHIFT, FPDATA, DRDY inactive LCD Enable Bit high to FPFRAME, FPLINE, FPSHIFT, FPDATA, DRDY active Min Max 1 1 2 Units TFPLINE TFPLINE Note Where TFPLINE is the period of FPLINE. Note The above timing assumes REG[1F0h] bit 4 is set to 1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 63 6.4.2 Power Save Status Power Save t1 LCD Power Save Status Bit t2 Memory Controller Power Save Status Bit not allowed not allowed t3 t4 t5 Memory Access Register Access allowed allowed allowed allowed Figure 6-13: Power Save Status Bits and Local Bus Memory Access Relative to Power Save Mode Note Memory access should not be performed after Power Save Mode has been initiated. Note Power Save is initiated through the Power Save Mode Enable bit (REG[1F0h] bit 0). Table 6-16 : Power Save Status and Local Bus Memory Access Relative to Power Save Mode Symbol t1 t2 t3 t4 t5 1. Parameter Power Save initiated to rising edge of LCD Power Save Status Power Save initiated to rising edge of Memory Controller Power Save Status Power Save deactivated to falling edge of LCD Power Save Status Power Save deactivated to falling edge of Memory Controller Power Save Status Falling edge of Memory Controller Power Save Status to the earliest time where memory access is allowed Min 1 Max 2 note 1 1 12 8 Units TFPLINE MCLK TFPFRAME MCLK MCLK t2max = The maximum value for t2 is based on the SDRAM Refresh Rate (REG[021h] bits 2:0) as follows. Table 6-17 : SDRAM Refresh Period Selection REG[021h] bits 2:0 000 001 010 011 SDRAM Refresh Period (MCLKs) 76 140 268 524 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 64 Epson Research and Development Vancouver Design Center 6.5 Display Interface 6.5.1 Single Monochrome 4-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[7:4] Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2 FPLINE MOD HDP FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 Invalid Invalid Invalid Invalid 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-317 1-318 1-319 1-320 Invalid Invalid Invalid Invalid HNDP * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6-14: Single Monochrome 4-Bit Panel Timing VDP = VNDP = HDP = HNDP = Vertical Display Period Vertical Non-Display Period Horizontal Display Period Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 65 Sync Timing FPFRAME t1 t2 t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[7:4] Figure 6-15: Single Monochrome 4-Bit Panel A.C. Timing Table 6-18 : Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[7:4] setup to FPSHIFT falling edge FPDAT[7:4] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 2 4 note 6 note 7 2 2 2 2 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. Ts 2. 3. 4. 5. 6. 7. = LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4 (see REG[014h]). t1min = t4min - 12 t4min = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] t5max = [((REG[034h] bits [4:0]) + 1) x 8 + 3] t6min = [((REG[034h] bits [4:0]) + 1) x 8 - 26] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 25] for 16 bpp color depth t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 15] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 14] for 16 bpp color depth t10min = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 66 Epson Research and Development Vancouver Design Center 6.5.2 Single Monochrome 8-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[7:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-16: Single Monochrome 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 67 t1 Sync Timing FPFRAME t3 t2 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 t14 1 2 FPDAT[7:0] Invalid Figure 6-17: Single Monochrome 8-Bit Panel A.C. Timing Table 6-19 : Single Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 4 8 note 6 note 7 4 4 4 4 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. 2. 3. 4. 5. 6. 7. = LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4 (see REG[014h]). t1min = t4min - 12 t4min = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] t5max = [((REG[034h] bits [4:0]) + 1) x 8 + 3] t6min = [((REG[034h] bits [4:0]) + 1) x 8 - 24] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 23] for 16 bpp color depth t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 13] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 12] for 16 bpp color depth t10min = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth Ts Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 68 Epson Research and Development Vancouver Design Center 6.5.3 Single Color 4-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[7:4] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 Invalid Invalid Invalid Invalid 1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-B319 1-R320 1-G320 1-B320 Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-18: Single Color 4-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 69 t1 Sync Timing FPFRAME t3 t2 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[7:4] Figure 6-19: Single Color 4-Bit Panel A.C. Timing Table 6-20 : Single Color 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[7:4] setup to FPSHIFT falling edge FPDAT[7:4] hold from FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 0.5 1 note 6 note 7 0.5 0.5 0.5 0.5 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. Ts 2. 3. 4. 5. 6. 7. = LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4 (see REG[014h]). t1min = t4min - 12 t4min = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] t5max = [((REG[034h] bits [4:0]) + 1) x 8 + 3] t6min = [((REG[034h] bits [4:0]) + 1) x 8 - 28.5] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 27.5] for 16 bpp color depth t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 17.5] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 16.5] for 16 bpp color depth t10min = 18 for 4 bpp or 8 bpp color depth = 17 for 16 bpp color depth Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 70 Epson Research and Development Vancouver Design Center 6.5.4 Single Color 8-Bit Panel Timing (Format 1) VDP VNDP FPFRAME FPLINE FPDAT[7:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE HDP HNDP FPSHIFT FPSHIFT2 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6 1-G6 1-R7 1-B7 1-G8 1-R9 1-B9 1-G10 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-B10 1-G11 1-B11 1-G12 1-R13 1-B13 1-G14 1-R15 1-B15 1-G16 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15 1-R16 1-B16 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-20: Single Color 8-Bit Panel Timing (Format 1) VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 71 Sync Timing FPFRAME t1 t2 t3 t4 FPLINE Data Timing FPLINE t5a t5b t8a t9 t6 t10 t7 t11 FPSHIFT t8b FPSHIFT2 t12 t13 t14 t15 FPDAT[7:0] Invalid 1 2 3 Figure 6-21: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 6-21 : Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol t1 t2 t3 t4 t5a t5b t6 t7 t8a t8b t9 t10 t11 t12 t13 t14 t15 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period FPSHIFT2 falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling, FPSHIFT2 rising edge FPSHIFT, FPSHIFT2 period FPSHIFT falling edge to FPLINE falling edge FPSHIFT2 falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high, FPSHIFT2 pulse width low FPSHIFT pulse width low, FPSHIFT2 pulse width high FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold from FPSHIFT falling edge FPDAT[7:0] setup to FPSHIFT2 falling edge FPDAT[7:0] hold from FPSHIFT2 falling edge Min note 2 12 11 note 3 note 4 note 5 t9 + 2 4 note 6 note 7 note 8 2 2 1 1 1 1 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts 1. 2. 3. 4. 5. 6. 7. 8. Ts = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). t1min = t4min - 12Ts t4min = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] t5amin= [((REG[034h] bits [4:0]) + 1) x 8 - 26] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 25] for 16 bpp color depth t5bmin= [((REG[034h] bits [4:0]) + 1) x 8 - 28] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 27] for 16 bpp color depth t8amin= [((REG[034h] bits [4:0]) + 1) x 8 - 17] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 16] for 16 bpp color depth t8bmin= [((REG[034h] bits [4:0]) + 1) x 8 - 15] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 14] for 16 bpp color depth t9min = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 72 Epson Research and Development Vancouver Design Center 6.5.5 Single Color 8-Bit Panel Timing (Format 2) VDP VNDP FPFRAME FPLINE MOD FPDAT[7:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-R5 1-G 5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 1-G638 1-B638 1-R639 1-G639 1-B639 1-R640 1-G640 1-B640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-22: Single Color 8-Bit Panel Timing (Format 2) VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 73 Sync Timing FPFRAME t1 t2 t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[7:0] Figure 6-23: Single Color 8-Bit Panel A.C. Timing (Format 2) Table 6-22 : Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 2 2 note 6 note 7 1 1 1 1 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. 2. 3. 4. 5. = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). = t3min - 12 = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] = [((REG[034h] bits [4:0]) + 1) x 8 + 3] = [((REG[034h] bits [4:0]) + 1) x 8 - 27] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 26] for or 16 bpp color depth 6. t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 16] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 15] for 16 bpp color depth 7. t10min = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth Ts t1min t3min t5max t6min Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 74 Epson Research and Development Vancouver Design Center 6.5.6 Single Color 16-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[15:0] Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT11 FPDAT10 FPDAT9 FPDAT8 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6 1-G6 1-R7 1-B7 1-G8 1-R9 1-B9 1-G10 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-B10 1-G11 1-B11 1-G12 1-R13 1-B13 1-G14 1-R15 1-B15 1-G16 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15 1-R16 1-B16 1-G635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-24: Single Color 16-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 75 Sync Timing FPFRAME t1 t2 t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[15:0] Figure 6-25: Single Color 16-Bit Panel A.C. Timing Table 6-23 : Single Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[15:0] setup to FPSHIFT falling edge FPDAT[15:0] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 3 5 note 6 note 7 2 2 2 2 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. 2. 3. 4. 5. 6. 7. Ts t1min t3min t5max t6min = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). = t3min - 12 = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] = [((REG[034h] bits [4:0]) + 1) x 8 + 3] = [((REG[034h] bits [4:0]) + 1) x 8 - 26] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 25] for 16 bpp color depth t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 15] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 14] for 16 bpp color depth t10min = 17 for 4 bpp or 8 bpp color depth = 16 for 16 bpp color depth Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 76 Epson Research and Development Vancouver Design Center 6.5.7 Dual Monochrome 8-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[7:0] Invalid LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 Invalid LINE 1/241 LINE 2/242 FPLINE MOD HDP HNDP FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-1 1-2 1-3 1-4 241-1 241-2 241-3 241-4 1-5 1-6 1-7 1-8 241-5 241-6 241-7 241-8 1-637 1-638 1-639 1-640 241-637 241-638 241-639 241-640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-26: Dual Monochrome 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:1]) = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 77 Sync Timing FPFRAME t1 t2 t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[7:0] Figure 6-27: Dual Monochrome 8-Bit Panel A.C. Timing Table 6-24 : Dual Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 t11 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width low FPSHIFT pulse width high FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 2 4 note 6 note 7 2 2 2 2 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. 2. 3. 4. 5. 6. 7. Ts t1min t3min t5max t6min = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). = t3min - 12 = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] = [((REG[034h] bits [4:0]) + 1) x 8 + 3] = [((REG[034h] bits [4:0]) + 1) x 8 - 18] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 17] for 16 bpp color depth t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 7] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 6] for 16 bpp color depth t10min = 9 for 4 bpp or 8 bpp color depth = 8 for 16 bpp color depth Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 78 Epson Research and Development Vancouver Design Center 6.5.8 Dual Color 8-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[7:0] Invalid LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 Invalid LINE 1/241 LINE 2/242 FPLINE MOD HDP HNDP FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R 3 1-G3 1-B 3 1-R4 1-G4 1-B4 1-R 5 1-G5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 1-B639 1-R640 1-G640 1-B640 2 41B639 241R640 241G640 2 41B640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 241-R 1 241-G2 241-B 3 241-R5 241-G6 241-B7 241-G1 24 1-B2 241-R 4 241-G 5 241-B6 241-R8 241-B1 241-R3 241-G4 241-B5 241-R7 241-G8 241-R 2 241-G3 241-B4 241-R 6 241-G7 241-B8 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-28: Dual Color 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) / 2 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 79 t1 t2 Sync Timing FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[7:0] Figure 6-29: Dual Color 8-Bit Panel A.C. Timing Table 6-25 : Dual Color 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 0.5 1 note 6 note 7 0.5 0.5 0.5 0.5 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. 2. 3. 4. 5. = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). = t3min - 12 = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] = [((REG[034h] bits [4:0]) + 1) x 8 + 3] = [((REG[034h] bits [4:0]) + 1) x 8 - 18.5] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 17.5] for 16 bpp color depth 6. t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 8.5] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 6.5] for 16 bpp color depth 7. t10min = 10 for 4 bpp or 8 bpp color depth = 9 for 16 bpp color depth Ts t1min t3min t5max t6min Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 80 Epson Research and Development Vancouver Design Center 6.5.9 Dual Color 16-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD FPDAT[15:0] Invalid LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 Invalid LINE 1/241 LINE 2/242 FPLINE MOD HDP HNDP FPSHIFT FPDAT[15,11] FPDAT[14,10] FPDAT[13,9] FPDAT[12,8] FPDAT[7,3] FPDAT[6,2] FPDAT[5,1] FPDAT[4,0] Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-R1, 241-R1 1-G1, 24 1-G 1 1-B1, 2 41-B 1 1-R2, 2 41-R 2 1-G2, 24 1-G 2 1-B2, 2 41-B 2 1-R3, 2 41-R 3 1-G3, 24 1-G 3 1-B3, 2 41-B 3 1-R4, 2 41 -R 4 1-G 4, 2 41-G 4 1-B4, 2 41-B 4 1-R5, 2 41 -R 5 1-G 5, 2 41-G 5 1-B 5, 2 41-B 5 1-R6, 2 41 -R 6 1-G6, 2 41-G6 1-B6, 2 41-B 6 1-R7, 2 41-R7 1-G7, 2 41-G7 1-B7, 241-B 7 1-R8, 2 41-R8 1-G8, 2 41-G8 1-B8, 241-B 8 1-G 63 8, 2 41-G 63 8 1-B 63 8, 241-B 638 1-R639 , 241 -R639 1-G 63 9, 2 41-G 63 9 1-B 63 9, 2 41-B63 9 1-R640 , 241 -R640 1-G 640, 2 41-G 64 0 1-B 64 0, 2 41-B64 0 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6-30: Dual Color 16-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) / 2 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 81 Sync Timing FPFRAME t1 t2 t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t10 t11 t8 t12 FPSHIFT t13 Invalid 1 t14 2 FPDAT[15:0] Figure 6-31: Dual Color 16-Bit Panel A.C. Timing Table 6-26 : Dual Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD transition to FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low FPDAT[15:0] setup to FPSHIFT falling edge FPDAT[15:0] hold to FPSHIFT falling edge Min note 2 12 11 note 3 3 note 5 t10 + 2 2 note 6 note 7 1 1 1 1 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts note 4 1. 2. 3. 4. 5. 6. 7. Ts t1min t3min t5max t6min = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). = t3min - 12 = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] = [((REG[034h] bits [4:0]) + 1) x 8 + 3] = [((REG[034h] bits [4:0]) + 1) x 8 - 19] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 18] for 16 bpp color depth t9min = [((REG[034h] bits [4:0]) + 1) x 8 - 8] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - 7] for 16 bpp color depth t10min = 9 for 4 bpp or 8 bpp color depth = 8 for 16 bpp color depth Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 82 Epson Research and Development Vancouver Design Center 6.5.10 TFT/D-TFD Panel Timing VNDP VDP FPFRAME FPLINE R[5:1], G[5:0], B[5:1] DRDY LINE480 Invalid LINE1 LINE480 Invalid FPLINE HNDP1 HDP HNDP2 FPSHIFT DRDY R[5:1] G [5:0] B[5:1] Invalid Invalid Invalid 1-1 1-1 1-1 1-2 1-2 1-2 1-640 1-640 1-640 Invalid Invalid Invalid Note: DRDY is used to indicate the first pixel Example Timing for 640x480 panel Figure 6-32: TFT/D-TFD Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1 = (REG[03Ah] bits [5:0]) + 1 = ((REG[032h] bits [6:0]) + 1) x 8Ts = HNDP1 + HNDP2 = ((REG[034h] bits [4:0]) + 1) x 8Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 83 t8 t9 FPFRAME t12 FPLINE t6 FPLINE t7 t17 t15 DRDY 1x Data Format t1 t2 t3 t11 t13 t14 t16 FPSHIFT t4 t5 1 2 t10 639 640 R[5:1] G[5:0] B[5:1] Invalid t27 t26 DRDY 2x Data Format t18 t19 t20 t21 t22 t14 t23 FPSHIFT t24 t25 3, 4 t10 637, 638 639, 640 R[5:1] G[5:0] B[5:1] Invalid 1, 2 Note: DRDY is used to indicate the active display Figure 6-33: TFT/D-TFD A.C. Timing Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 84 Epson Research and Development Vancouver Design Center Table 6-27 : TFT/D-TFD A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 Parameter FPSHIFT period FPSHIFT pulse width high FPSHIFT pulse width low data setup to FPSHIFT falling edge data hold from FPSHIFT falling edge FPLINE cycle time FPLINE pulse width low FPFRAME cycle time FPFRAME pulse width low horizontal display period FPLINE setup to FPSHIFT falling edge FPFRAME falling edge to FPLINE falling edge phase difference DRDY to FPSHIFT falling edge setup time DRDY pulse width DRDY falling edge to FPLINE falling edge (1x) DRDY hold from FPSHIFT falling edge FPLINE Falling edge to DRDY active (1x) FPSHIFT period FPSHIFT pulse width high FPSHIFT pulse width low FPLINE setup to FPSHIFT falling edge DRDY to FPSHIFT falling edge setup time DRDY hold from FPSHIFT falling edge data setup to FPSHIFT falling edge data hold from FPSHIFT falling edge FPLINE Falling edge to DRDY active (2x) DRDY falling edge to FPLINE falling edge (2x) Min 1 0.45 0.45 0.45 0.45 note 2 note 3 note 4 note 5 note 6 0.45 note 7 0.45 note 8 note 9 0.45 note 10 2 1 1 note 11 1 1 1 1 note 12 note 13 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts lines lines Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Ts = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]). t6min = [((REG[032h] bits [6:0]) + 1) x 8 + ((REG[034h] bits [4:0]) + 1) x 8] t7min = [((REG[036h] bits [3:0]) + 1) x 8] t8 min = [((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) + ((REG[03Ah] bits [5:0]) + 1)] t9min = [((REG[03Ch] bits [2:0]) + 1)] t10min = [((REG[032h] bits [6:0]) + 1) x 8] t12min= [(REG[035h] bits [4:0]) x 8 + 1] t14min= [((REG[032h] bits [6:0]) + 1) x 8] t15min= [(REG[035h] bits [4:0]) x 8 + 5] for 4 bpp or 8 bpp color depth = [(REG[035h] bits [4:0]) x 8 + 6] for 16 bpp color depth t17min= [((REG[034h] bits [4:0]) + 1) x 8 - (REG[035h] bits [4:0]) x 8 - 5] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - (REG[035h] bits [4:0]) x 8 - 6] for 16 bpp color depth t21min= 1 for 4 bpp or 8 bpp color depth = 0 for 16 bpp color depth t26min= [((REG[034h] bits [4:0]) + 1) x 8 - (REG[035h] bits [4:0]) x 8 - 4] for 4 bpp or 8 bpp color depth = [((REG[034h] bits [4:0]) + 1) x 8 - (REG[035h] bits [4:0]) x 8 - 5] for 16 bpp color depth t27min= [(REG[035h] bits [4:0]) x 8 + 4] for 4 bpp or 8 bpp color depth = [(REG[035h] bits [4:0]) x 8 + 5] for 16 bpp color depth S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 85 6.5.11 CRT Timing VNDP VDP VRTC HRTC RED,GREEN,BLUE LINE480 LINE1 LINE480 HRTC HNDP1 HDP HNDP2 1-640 RED,GREEN,BLUE 1-1 1-2 Example Timing for 640x480 CRT Figure 6-34: CRT Timing VDP VNDP HDP HNDP HNDP2 = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = HRTC Start Position = (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1 = (REG[058h] bits [6:0]) + 1 = ((REG[050h] bits [6:0]) + 1) x 8Ts = HNDP1 + HNDP2 = ((REG[052h] bits [5:0]) + 1) x 8Ts = (REG[053h] bits [5:0]) x 8 + 4Ts for 4/8 bpp = (REG[053h] bits [5:0]) x 8 + 5Ts for 16 bpp Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 86 Epson Research and Development Vancouver Design Center t1 t2 VRTC t3 HRTC Figure 6-35: CRT A.C. Timing Table 6-28 : CRT A.C. Timing Symbol t1 t2 t3 VRTC cycle time VRTC pulse width low VRTC falling edge to FPLINE falling edge phase difference Parameter Min Typ note 1 note 2 note 3 Max Units lines lines Ts 1. 2. 3. t1 t2 t3 = [((REG[057h] bits 1:0, REG[056h] bits 7:0) + 1) + ((REG[058h] bits 6:0) + 1)] = [((REG[05Ah] bits 2:0) + 1)] = [((REG[053h] bits 4:0) + 1) x 8] S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 87 6.6 TV Timing 6.6.1 TV Output Timing The overall NTSC and PAL video timing is shown in Figure 6-36: and Figure 6-37: respectively. Register Programming: Vertical Non-Display Period = 20 VRTC Start Position = 0 Field 1 vertical blanking interval = 20 lines 261 262 1 2 pre-equalizing pulse interval 3 4 5 vertical sync pulse interval 6 7 8 9 10 19 20 21 post-equalizing pulse interval start of field 1 VNDP TV VRTC Start Position (field 1) 261 Field 2 start of field 2 VNDP TV VRTC Start Position (field 2) Start of Vertical Sync 262 263 1 2 3 4 5 6 7 8 9 10 19 20 21 Figure 6-36: NTSC Video Timing Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 88 Epson Research and Development Vancouver Design Center Register Programming: Vertical Non-Display Period = 26 VRTC Start Position = 0 Field 1 vertical blanking interval = 25 lines 620 621 622 623 624 625 pre-equalizing pulse interval 1 2 3 4 5 6 7 21 22 23 24 vertical sync pulse interval post-equalizing pulse interval start of field 1 VNDP TV VRTC Start Position (field 1) 308 309 310 311 312 313 314 315 316 317 318 319 320 Field 2 start of field 2 VNDP TV VRTC Start Position (field 2) 620 621 622 623 624 625 Field 3 1 2 3 4 5 6 7 334 335 336 21 22 23 24 start of field 3 VNDP TV VRTC Start Position (field 3) 308 309 310 311 312 313 314 315 316 317 318 319 320 Field 4 start of field 4 VNDP TV VRTC Start Position (field 4) 334 335 336 Start of Vertical Sync Figure 6-37: PAL Video Timing S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 89 IRE 100 Active Line 20 0 -20 -40 t1 t2 t6 t8 t9 0 t10 Blanking Level t3 t4 t5 t7 40 IRE Blanking Level Equalizing Pulse Vertical Sync Pulse t11 Start of Horizontal Sync -40 Figure 6-38: Horizontal Timing for NTSC/PAL Table 6-29 : Horizontal Timing for NTSC/PAL Symbol T4SC t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Parameter (4x Subcarrier clock) period Front Porch Horizontal Sync Breezeway Color Burst Color Back Porch Horizontal Blanking Active Video Line Period Half Line Period Equalizing Pulse Vertical Serration NTSC 69.841 note 1 67 9 39 note 2 note 4 note 6 910 455 33 67 PAL 56.387 note 1 83 16 44 note 3 note 5 note 6 1135 568 / 567 41 83 Units ns T4SC T4SC T4SC T4SC T4SC T4SC T4SC T4SC T4SC T4SC T4SC 1. 2. 3. t1 t5NTSC t5PAL 4. t6NTSC 5. t6PAL 6. t7 Important: REG[050] and REG[052] must be programmed to satisfy the Line Period (t8). For NTSC, (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 6) = 910. For PAL, (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 7) = 1135. = ((REG[053] bits[5:0]) + 1) x 8 - 6 (4bpp, 8bpp modes) = ((REG[053] bits[5:0]) + 1) x 8 - 5 (16bpp mode) = (((REG[052] bits[5:0]) x 8) + 6) - (((REG[053] bits[5:0]) + 1) x 8) - 109 (4bpp, 8bpp modes) = (((REG[052] bits[5:0]) x 8) + 6) - (((REG[053] bits[5:0]) + 1) x 8) - 110 (16bpp mode) = (((REG[052] bits[5:0]) x 8) + 7) - (((REG[053] bits[5:0]) + 1) x 8) - 137 (4bpp, 8bpp modes) = (((REG[052] bits[5:0]) x 8) + 7) - (((REG[053] bits[5:0]) + 1) x 8) - 138 (16bpp mode) = ((REG[052] bits[5:0]) x 8) + 6 = ((REG[052] bits[5:0]) x 8) + 7 = ((REG[050] bits[6:0]) + 1) x 8 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 90 Epson Research and Development Vancouver Design Center 0 Vertical Non-Display Period NTSC Odd Field 1 PAL Odd Fields 1,3 Vertical Display Period t4 Vertical Sync t2 909 (NTSC) 1134 (PAL) t1 Even Lines t5 Vertical Non-Display Period NTSC Even Field 2 PAL Even Fields 2,4 t4 Vertical Sync t3 Vertical Display Period t1 Odd Lines Horizontal Sync Figure 6-39: Vertical Timing for NTSC/PAL Table 6-30 : Vertical Timing for NTSC/PAL Symbol TLINE t1 t2 t3 t4 t5 Parameter Line Period Vertical Field Period Vertical Even Blanking Vertical Odd Blanking Vertical Sync Position Frame Period NTSC 63.55556 note 1 note 2 note 3 note 4 525 PAL 63.99964 note 1 note 2 note 3 note 5 625 Units us TLINE TLINE TLINE TLINE TLINE 1. t1 2. t2 3. t3 4. t4NTSC 5. t4PAL = ({(REG[057h] bits[1:0]), (REG[056] bits[7:0])} + 1) / 2 (rounded up) = ((REG[058h] bits[6:0]) + 1) for NTSC field 1 = ((REG[058h] bits [6:0]) + 2) for PAL fields 1 and 3 = ((REG[058h] bits[6:0]) + 2) for NTSC field 2 = ((REG[058h] bits [6:0]) + 1) for PAL fields 2 and 4 = ((REG[059h] bits[6:0]) + 4) for field 1 = ((REG[059h] bits[6:0]) + 4.5) for field 2 = ((REG[059h] bits[6:0]) + 5) for field 1 and field 3 = ((REG[059h] bits[6:0]) + 4.5) for field 2 and field 4 Important REG[056], REG[057], and REG[058] must be programmed to satisfy the Frame Period (t5). For NTSC, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) x 2 + 1) = 525 For PAL, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) x 2 + 1) = 625. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 91 6.7 MediaPlug Interface Timing T1 VMPCLK t2 VMPCLKN t4 VMPDIN[3:0] t5 VMPCTRL VMPLCTRL t7 VMPDout t8 t6 t3 Figure 6-40: MediaPlug A.C. Timing Note The above timing diagram assumes no load. Table 6-31: MediaPlug A.C. Timing Symbol T1 t2 t3 t4 t5 t6 t7 t8 VMPCLK clock period VMPCLK falling edge to VMPCLKN rising edge skew VMPCLKN falling edge to VMPCLK rising edge skew Input data setup VMPCTRL setup Local control signal delay from VMPCLK falling edge Output data delay from VMPCLK falling edge Output data tristate delay from VMPCLK falling edge Parameter Min 50 0.1 .3 17 16 0 0 0.4 1.1 1.1 1.4 0.6 1.1 Max Units ns ns ns ns ns ns ns ns Note VMPCLK, VMPCLKN are twice the period of the MediaPlug Clock. See Section 7, "Clocks" on page 92. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 92 Epson Research and Development Vancouver Design Center 7 Clocks 7.1 Clock Overview The following diagram provides a logical representation of the S1D13806 internal clocks. CLKI BUSCLK /2 0 1 BCLK (See "CPU Interface Timing" on page 40 for Max) 00 0 01 /2 1 CNF5 CLKI3 Reserved 10 11 MCLK (50MHz Max) 00 REG[010h] bit 4 01 REG[010h] bit 1,0 CLKI2 10 11 /2 /3 /4 00 01 10 11 LCD PCLK (65MHz Max) REG[014h] bits 1,0 REG[014h] bits 5,4 00 01 10 11 /2 /3 /4 00 01 10 11 CRT/TV PCLK (65MHz Max) REG[018h] bits 1,0 00 01 10 11 REG[018h] bits 5,4 00 /2 /3 /4 01 10 11 MediaPlug Clock (20MHz Max) REG[01Ch] bits 1,0 REG[01Ch] bits 5,4 Figure 7-1: Clock Overview Diagram S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 93 7.2 Clock Descriptions 7.2.1 MCLK MCLK should be configured as close to its maximum (50MHz) as possible. The S1D13806 contains sophisticated clock management, therefore, very little power is saved by reducing the MCLK frequency. The frequency of MCLK is directly proportional to the bandwidth of the video memory. The bandwidth available to the CPU (for screen updates) is that left over after screen refresh takes its share. CPU bandwidth can be seriously reduced when the MCLK frequency is reduced, especially for high-resolution, high-color modes where screen refresh has high bandwidth requirements. 7.2.2 LCD PCLK LCD PCLK should be chosen to match the optimum frame rate of the panel. See Section 18, "Clocking" on page 189 for details on the relationship between PCLK and frame rate, and for the maximum supportable PCLK frequencies for any given video mode. Some flexibility is possible in the selection of PCLK. Firstly, panels typically have a range of permissible frame rates. Secondly, it may be possible to choose a higher PCLK frequency and tailor the horizontal non-display period (see REG[052h]) to bring down the frame-rate to its optimal value. 7.2.3 CRT/TV PCLK TVs and older CRTs usually have very precise frequency requirements, so it may be necessary to dedicate one of the clock inputs to this function. More recent CRTs work within a range of frequencies, so it may be possible to support them with the BUSCLK or MCLK. 7.2.4 MediaPlug Clock The MediaPlug Clock frequency is internally divided by 2 to provide the output signals VMPCLK and VMPCLKN for the MediaPlug interface. VMPCLK requires a clock in the range of 6-8MHz, therefore the MediaPlug Clock must be in the range of 12-16MHz. For AC timing see Section 6.7, "MediaPlug Interface Timing" on page 91. MediaPlug Clock (12-16MHz) /2 VMPCLK (6-8MHz) VMPCLKN (6-8MHz) Figure 7-2: MediaPlug Clock Output Signals Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 94 Epson Research and Development Vancouver Design Center 7.3 Clock Selection Table 7-1 : Clock Selection Clock Source Options CLKI CLKI / 2 CLKI / 3 CLKI / 4 CLKI2 CLKI2 / 2 External Clocks CLKI2 / 3 CLKI2 / 4 CLKI3 CLKI3 / 2 BUSCLK BUSCLK / 2 BUSCLK / 3 BUSCLK / 4 MCLK2 MCLK / 22 MCLK / MCLK / 32 42 Internal Clocks MCLK REG[010h] = 00h REG[010h] = 10h -- -- -- -- -- -- REG[010h] = 02h REG[010h] = 12h REG[010h] = 01h REG[010h] = 11h -- -- -- -- -- -- LCD PCLK REG[014h] = 00h REG[014h] = 10h REG[014h] = 20h REG[014h] = 30h REG[014h] = 02h REG[014h] = 12h REG[014h] = 22h REG[014h] = 32h -- -- REG[014h] = 01h REG[014h] = 11h REG[014h] = 21h REG[014h] = 31h REG[014h] = 03h REG[014h] = 13h REG[014h] = 23h REG[014h] = 33h CRT/TV PCLK1 REG[018h] = 00h REG[018h] = 10h REG[018h] = 20h REG[018h] = 30h REG[018h] = 02h REG[018h] = 12h REG[018h] = 22h REG[018h] = 32h -- -- REG[018h] = 01h REG[018h] = 11h REG[018h] = 21h REG[018h] = 31h REG[018h] = 03h REG[018h] = 13h REG[018h] = 23h REG[018h] = 33h MediaPlug Clock REG[01Ch] = 00h REG[01Ch] = 10h REG[01Ch] = 20h REG[01Ch] = 30h REG[01Ch] = 02h REG[01Ch] = 12h REG[01Ch] = 22h REG[01Ch] = 32h -- -- REG[01Ch] = 01h REG[01Ch] = 11h REG[01Ch] = 21h REG[01Ch] = 31h REG[01Ch] = 03h REG[01Ch] = 13h REG[01Ch] = 23h REG[01Ch] = 33h Note 1. The CRT/TV pixel clock may be further multiplied by 2 when TV with Flicker Filter is enabled using REG[018h] bit 7. 2. MCLK may be a previously divided down version of CLKI, CLKI3, or BUSCLK. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 95 7.4 Clocks vs. Functions The S1D13806 has five clock signals. Not all clock signals must be active for certain functions to be carried out. The following table shows which clocks are required for each function. Table 7-2: Clocks vs. Functions Function Register read/write LCD LUT read/write CRT/TV LUT read/write Memory read/write 2D Operation MediaPlug Registers read/write Power Save Mode Required Clocks1 BUSCLK Yes2 Yes Yes Yes Yes Yes LCD PCLK No Yes ----CRT/TV PCLK No -Yes ---MCLK No --Yes3 Yes -MediaPlug Clock No ----Yes see Section 19, "Power Save Mode" on page 202 Note 1 The S1D13806 contains sophisticated power management that dynamically shuts down clocks when not required. 2 Before turning off the BUSCLK source externally, wait a minimum of 3 BUSCLK after a register read and a minimum of 4 BUSCLK after a register write. 3 Before turning off the MCLK source externally, wait a minimum of 6 MCLK after a memory read and a minimum of 16 MCLK after a memory write. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 96 Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13806 registers. It also provides detailed information about the layout and usage of each register. 8.1 Initializing the S1D13806 Before programming the S1D13806 registers, the following bits must be set. * Register/Memory Select bit (REG[001h] bit 7) * SDRAM Initialization bit (REG[020h] bit 7) 8.1.1 Register Memory Select Bit At reset, the Register/Memory Select bit is set to 1. This means that only REG[000h] (readonly) and REG[001h] are accessible until a write to REG[001h] sets bit 7 to 0 making all registers and memory accessible. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging. 8.1.2 SDRAM Initialization Bit To initialize the embedded SDRAM in the S1D13806, this bit must be set to 1 a minimum of 200s after reset. This bit must be set to 1 before memory access is performed. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 97 8.2 Register Mapping The S1D13806 registers are memory-mapped. When the system decodes the input pins as CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by A[20:0]. When A20 = 1 the BitBLT data register ports are decoded allowing the system to access the display buffer through the 2D BitBLT engine using address lines A[19:0]. When A20 = 0 and A12 = 0 the registers are decoded using A[8:0] as an index. When A20 = 0 and A12 = 1 the MediaPlug register ports are decoded using A[11:0]. The MediaPlug register ports are defined only when the configuration input CONF7 = 1 on reset. When CONF7 = 0 on reset, A12 is always treated as 0 and the MediaPlug register space is not available - see Table 4-9, "Summary of Power-On/Reset Options," on page 33. Table 8-1, "Register Mapping with CS# = 0 and M/R# = 0" shows the decoding for each register type. Table 8-1 : Register Mapping with CS# = 0 and M/R# = 0 Register Types (Range) BitBLT data registers (1M byte) MediaPlug registers (4K bytes) On-chip registers (512 bytes) Address A20-A0 Decoding 10 0000 to 1F FFFFh 1000h to 1FFFh 0 to 1FFh Note The registers may be aliased within the allocated register space. If aliasing is undesirable, the register space must be fully decoded. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 98 Epson Research and Development Vancouver Design Center 8.3 Register Set The S1D13806 register set is as follows. Table 8-2 : S1D13806 Register Set Register REG[000h] Revision Code Register Pg Basic Registers 101 Register REG[001h] Miscellaneous Register Pg 101 General IO Pins Registers REG[004h] General IO Pins Configuration Register 0 REG[008h] General IO Pins Control Register 0 102 102 REG[005h] General IO Pins Configuration Register 1 REG[009h] General IO Pins Control Register 1 102 103 Configuration Readback Register REG[00Ch] Configuration Status Register 103 Clock Configuration Registers REG[010h] Memory Clock Configuration Register REG[018h] CRT/TV Pixel Clock Configuration Register REG[01Eh] CPU To memory Wait State Select Register 103 105 107 REG[014h] LCD Pixel Clock Configuration Register REG[01Ch] MediaPlug Clock Configuration Register 104 106 Memory Configuration Registers REG[020h] Memory Configuration Register REG[02Ah] SDRAM Timing Control Register 0 108 109 REG[021h] SDRAM Refresh Rate Register REG[02Bh] SDRAM Timing Control Register 1 109 109 Panel Configuration Registers REG[030h] Panel Type Register REG[032h] LCD Horizontal Display Width Register REG[036h] TFT FPLINE Pulse Width Register REG[039h] LCD Vertical Display Height Register 1 REG[03Bh] TFT FPFRAME Start Position Register 110 111 113 113 114 REG[031h] MOD Rate Register REG[034h] LCD Horizontal Non-Display Period Register REG[038h] LCD Vertical Display Height Register 0 REG[03Ah] LCD Vertical Non-Display Period Register REG[03Ch] TFT FPFRAME Pulse Width Register 111 112 113 114 115 LCD Display Mode Registers REG[040h] LCD Display Mode Register REG[042h] LCD Display Start Address Register 0 REG[044h] LCD Display Start Address Register 2 REG[047h] LCD Memory Address Offset Register 1 115 118 118 118 REG[041h] LCD Miscellaneous Register REG[043h] LCD Display Start Address Register 1 REG[046h] LCD Memory Address Offset Register 0 REG[048h] LCD Pixel Panning Register 117 118 118 119 REG[04Ah] LCD Display FIFO High Threshold Control Register119 REG[04Bh] LCD Display FIFO Low Threshold Control Register 120 CRT/TV Configuration Registers REG[050h] CRT/TV Horizontal Display Width Register REG[053h] CRT/TV HRTC Start Position Register REG[056h] CRT/TV Vertical Display Height Register 0 REG[058h] CRT/TV Vertical Non-Display Period Register REG[05Ah] CRT VRTC Pulse Width Register 120 121 122 122 123 REG[052h] CRT/TV Horizontal Non-Display Period Register REG[054h] CRT/TV HRTC Pulse Width Register REG[057h] CRT/TV Vertical Display Height Register 1 REG[059h] CRT/TV VRTC Start Position Register REG[05Bh] TV Output Control Register 120 121 122 123 124 CRT/TV Display Mode Registers REG[060h] CRT/TV Display Mode Register REG[063h] CRT/TV Display Start Address Register 1 REG[066h] CRT/TV Memory Address Offset Register 0 REG[068h] CRT/TV Pixel Panning Register REG[06Bh] CRT/TV FIFO Low Threshold Control Register 125 126 126 127 128 REG[062h] CRT/TV Display Start Address Register 0 REG[064h] CRT/TV Display Start Address Register 2 REG[067h] CRT/TV Memory Address Offset Register 1 REG[06Ah] CRT/TV FIFO High Threshold Control Register 126 126 126 127 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 99 Table 8-2 : S1D13806 Register Set Register REG[070h] LCD Ink/Cursor Control Register REG[072h] LCD Cursor X Position Register 0 REG[074h] LCD Cursor Y Position Register 0 REG[076h] LCD Ink/Cursor Blue Color 0 Register REG[078h] LCD Ink/Cursor Red Color 0 Register REG[07Bh] LCD Ink/Cursor Green Color 1 Register REG[07Eh] LCD Ink/Cursor FIFO High Threshold Register Pg LCD Ink/Cursor Registers 128 129 130 130 131 131 132 Register REG[071h] LCD Ink/Cursor Start Address Register REG[073h] LCD Cursor X Position Register 1 REG[075h] LCD Cursor Y Position Register 1 REG[077h] LCD Ink/Cursor Green Color 0 Register REG[07Ah] LCD Ink/Cursor Blue Color 1 Register REG[07Ch] LCD Ink/Cursor Red Color 1 Register Pg 129 129 130 131 131 131 CRT/TV Ink/Cursor Registers REG[080h] CRT/TV Ink/Cursor Control Register REG[082h] CRT/TV Cursor X Position Register 0 REG[084h] CRT/TV Cursor Y Position Register 0 REG[086h] CRT/TV Ink/Cursor Blue Color 0 Register REG[088h] CRT/TV Ink/Cursor Red Color 0 Register REG[08Bh] CRT/TV Ink/Cursor Green Color 1 Register 132 133 134 135 135 135 REG[081h] CRT/TV Ink/Cursor Start Address Register REG[083h] CRT/TV Cursor X Position Register 1 REG[085h] CRT/TV Cursor Y Position Register 1 REG[087h] CRT/TV Ink/Cursor Green Color 0 Register REG[08Ah] CRT/TV Ink/Cursor Blue Color 1 Register REG[08Ch] CRT/TV Ink/Cursor Red Color 1 Register 133 133 134 135 135 136 REG[08Eh] CRT/TV Ink/Cursor FIFO High Threshold Register 136 BitBLT Configuration Registers REG[100h] BitBLT Control Register 0 REG[102h] BitBLT ROP Code/Color Expansion Register REG[104h] BitBLT Source Start Address Register 0 REG[106h] BitBLT Source Start Address Register 2 REG[109h] BitBLT Destination Start Address Register 1 REG[10Ch] BitBLT Memory Address Offset Register 0 REG[110h] BitBLT Width Register 0 REG[112h] BitBLT Height Register 0 REG[114h] BitBLT Background Color Register 0 REG[118h] BitBLT Foreground Color Register 0 137 139 141 141 142 142 143 143 144 144 REG[101h] BitBLT Control Register 1 REG[103h] BitBLT Operation Register REG[105h] BitBLT Source Start Address Register 1 REG[108h] BitBLT Destination Start Address Register 0 REG[10Ah] BitBLT Destination Start Address Register 2 REG[10Dh] BitBLT Memory Address Offset Register 1 REG[111h] BitBLT Width Register 1 REG[113h] BitBLT Height Register 1 REG[115h] BitBLT Background Color Register 1 REG[119h] BitBLT Foreground Color Register 1 138 140 141 142 142 142 143 143 144 144 Look-Up Table Registers REG[1E0h] Look-Up Table Mode Register REG[1E4h] Look-Up Table Data Register 145 146 REG[1E2h] Look-Up Table Address Register 145 Power Save Configuration Registers REG[1F0h] Power Save Configuration Register 146 REG[1F1h] Power Save Status Register 147 Miscellaneous Register REG[1F4h] CPU-To-Memory Access Watchdog Timer Register 148 Common Display Mode Register REG[1FCh] Display Mode Register 149 MediaPlug Control Registers REG[1000h] MediaPlug LCMD Register REG[1004h] MediaPlug CMD Register 150 153 REG[1002h] MediaPlug Reserved LCMD Register REG[1006h] MediaPlug Reserved CMD Register 153 154 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 100 Epson Research and Development Vancouver Design Center Table 8-2 : S1D13806 Register Set Register REG[1008h] to REG[1FFEh] MediaPlug Data Registers Pg MediaPlug Data Registers 155 Register Pg BitBLT Data Registers REG[100000h] to REG[1FFFFEh] BitBLT Data Registers 155 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 101 8.4 Register Descriptions 8.4.1 Basic Registers Revision Code Register REG[000h] Product Code Product Code Product Code Product Code Product Code Product Code Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Revision Code Bit 1 RO Revision Code Bit 0 bits 7-2 Product Code Bits [5:0] This read-only register indicates the product code of the controller. The product code for S1D13806 is 000111b. Revision Code Bits [1:0] This read-only register indicates the revision code of the controller. The revision code is 00b. bits 1-0 Miscellaneous Register REG[001h] Register/ Memory Select n/a n/a n/a n/a Reserved Reserved RW Reserved bit 7 Register/Memory Select Bit At reset, the Register/Memory Select bit is set to 1. This means that only REG[000h] (read-only) and REG[001h] are accessible until a write to REG[001h] sets bit 7 to 0 making all registers and memory accessible. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging. Reserved. This bit must be set to 0. Reserved. This bit must be set to 0. Reserved. This bit must be set to 0. bit 2 bit 1 bit 0 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 102 Epson Research and Development Vancouver Design Center 8.4.2 General IO Pins Registers General IO Pins Configuration Register 0 REG[004h] GPIO7 Pin IO Config. GPIO6 Pin IO Config. GPIO5 Pin IO Config. GPIO4 Pin IO Config. GPIO3 Pin IO Config. GPIO2 Pin IO Config. GPIO1 Pin IO Config. RW GPIO0 Pin IO Config. bit 7-0 GPIO[7:0] Pin IO Configuration Bits When bit n = 1, GPIO[n] is configured as an output pin. (where n ranges from 0 to 7) When bit n = 0 (default), GPIO[n] is configured as an input pin. (where n ranges from 0 to 7). General IO Pins Configuration Register 1 REG[005h] n/a n/a n/a GPIO12 Pin IO Config. GPIO11 Pin IO Config. GPIO10 Pin IO Config. GPIO9 Pin IO Config. RW GPIO8 Pin IO Config. bit 4-0 GPIO[12:8] Pin IO Configuration Bits When bit n = 1, GPIO[n+8] is configured as an output pin. (where n ranges from 0 to 4) When bit n = 0 (default), GPIO[n+8] is configured as an input pin. (where n ranges from 0 to 4) Note Note that CONF7 must be properly configured at the rising edge of RESET# to enable GPIO12 as an IO pin, otherwise GPIO12 is used for the Media Plug interface and this register has no effect. The following table shows GPIO12 usage. Table 8-3 : Media Plug/GPIO12 Pin Functionality Pin GPIO12 CONF7 on Reset 0 GPIO12 1 VMPEPWR General IO Pins Control Register 0 REG[008h] GPIO7 Pin IO Status GPIO6 Pin IO Status GPIO5 Pin IO Status GPIO4Pin IO Status GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status RW GPIO0 Pin IO Status bit 7-0 GPIO[7:0] Pin IO Status Bits When GPIO[n] is configured as an output, writing a 1 to bit n drives GPIO[n] high and writing a 0 to this bit drives GPIO[n] low. (n ranges from 0 to 7) When GPIO[n] is configured as an input, a read from bit n returns the status of GPIO[n]. (n ranges from 0 to 7) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 103 General IO Pins Control Register 1 REG[009h] n/a n/a n/a GPIO12 Pin IO Status GPIO11 Pin IO Status GPIO10 Pin IO Status GPIO9 Pin IO Status RW GPIO8 Pin IO Status bit 4-0 GPIO[12:8] Pin IO Status Bits When GPIO[n+8] is configured as an output, writing a 1 to bit n drives GPIO[n+8] high and writing a 0 to this bit drives GPIO[n+8] low. (n ranges from 0 to 4) When GPIO[n+8] is configured as an input, a read from bit n+8 returns the status of GPIO[n+8]. (n ranges from 0 to 4) Note CONF7 must be properly configured at the rising edge of RESET# to enable GPIO12 as an IO pin, otherwise GPIO12 is used for the Media Plug interface and this register has no effect on GPIO12. See Table 8-3, "Media Plug/GPIO12 Pin Functionality" for GPIO12 usage. 8.4.3 Configuration Readback Register Configuration Status Register REG[00Ch] RO CONF[7] CONF[6] CONF[5] CONF[4] CONF[3] CONF[2] CONF[1] CONF[0] Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status bits 7-0 CONF[7:0] Configuration Status Bits These read-only bits return the status of CONF[7:0] at the rising edge of RESET#. 8.4.4 Clock Configuration Registers Memory Clock Configuration Register REG[010h] n/a n/a n/a MCLK Divide Select n/a n/a RW MCLK Source MCLK Source Select Bit 1 Select Bit 0 Note For further information on MCLK, see Section 7.2, "Clock Descriptions" on page 93. bit 4 MCLK Divide Select When this bit = 1, the internal memory clock (MCLK) frequency is half of the MCLK source frequency. When this bit = 0, the memory clock frequency is equal to the MCLK source frequency. Note The MCLK frequency should always be set to the maximum frequency allowed by the SDRAM. This provides maximum performance and minimizes overall system power consumption. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 104 Epson Research and Development Vancouver Design Center bit 1-0 MCLK Source Select Bits [1:0] These bits determine the source of the internal memory clock (MCLK). Table 8-4 : MCLK Source Select MCLK Source Select Bits 00 01 10 11 MCLK Source CLKI BUSCLK CLKI3 Reserved Note The MCLK Divide Select bit must be set to 1 before changing the MCLK Source Select bits. LCD Pixel Clock Configuration Register REG[014h] n/a n/a LCD PCLK Divide Select Bit 1 LCD PCLK Divide Select Bit 0 n/a n/a RW LCD PCLK LCD PCLK Source Select Source Select Bit 1 Bit 0 Note For further information on the LCD PCLK, refer to Section 7.2, "Clock Descriptions" on page 93. bits 5-4 LCD PCLK Divide Select Bits [1:0] These bits determine the divide used to generate the LCD pixel clock from the LCD pixel clock source. Table 8-5 : LCD PCLK Divide Selection LCD PCLK Divide Select Bits 00 01 10 11 LCD PCLK Source to LPCLK Frequency Ratio 1:1 2:1 3:1 4:1 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 105 bits 1-0 LCD PCLK Source Select Bits [1:0] These bits determine the source of the pixel clock for the LCD display. Table 8-6 : LCD PCLK Source Selection LCD PCLK Source Select Bits 00 01 10 11 LCD PCLK Source CLKI BUSCLK CLKI2 MCLK Note MCLK may be a previously divided down version of CLKI, CLKI3, or BUSCLK. CRT/TV Pixel Clock Configuration Register REG[018h] Flicker Filter Clock Enable n/a CRT/TV PCLK Divide Select Bit 1 CRT/TV PCLK Divide Select Bit 0 n/a n/a CRT/TV PCLK Source Select Bit 1 RW CRT/TV PCLK Source Select Bit 0 Note For further information on the CRT/TV PCLK, refer to Section 7.2, "Clock Descriptions" on page 93. bit 7 Flicker Filter Clock Enable This bit must be set to 1 when TV with flicker filter is enabled. For details on TV with flicker filter, see REG[1FCh] bits 2-0. CRT/TV PCLK Divide Select Bits[1:0] These bits determine the divide used to generate the CRT/TV pixel clock from the CRT/TV pixel clock source. Table 8-7 : CRT/TV PCLK Divide Selection CRT/TV PCLK Divide Select Bits 00 01 10 11 CRT/TV PCLK Source to DPCLK Frequency Ratio 1:1 2:1 3:1 4:1 bits 5-4 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 106 Epson Research and Development Vancouver Design Center bits 1-0 CRT/TV PCLK Source Select Bits [1:0] These bits determine the source of the pixel clock for the CRT/TV display. Table 8-8 : CRT/TV PCLK Source Selection CRT/TV PCLK Source Select Bits 00 01 10 11 CRT/TV PCLK Source CLKI BUSCLK CLKI2 MCLK Note MCLK may be a previously divided down version of CLKI, CLKI3, or BUSCLK. MediaPlug Clock Configuration Register REG[01Ch] n/a n/a MediaPlug Clock Divide Select Bit 1 MediaPlug Clock Divide Select Bit 0 n/a n/a MediaPlug Clock Source Select Bit 1 RW MediaPlug Clock Source Select Bit 0 Note For further information on the MediaPlug Clock, refer to Section 7.2, "Clock Descriptions" on page 93. bits 5-4 MediaPlug Clock Divide Select Bits [1:0] These bits determine the divide used to generate the MediaPlug Clock from the MediaPlug Clock source. Table 8-9 : MediaPlug Clock Divide Selection MediaPlug Clock Divide Select Bits 00 01 10 11 MediaPlug Clock Source to MediaPlug Clock Frequency Ratio 1:1 2:1 3:1 4:1 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 107 bits 1-0 MediaPlug Clock Source Select Bits [1:0] These bits determine the source of the MediaPlug Clock for the MediaPlug Interface. See Section 6.7, "MediaPlug Interface Timing" on page 91 for AC Timing. Table 8-10 : MediaPlug Clock Source Selection MediaPlug Clock Source Select Bits 00 01 10 11 MediaPlug Clock Source CLKI BUSCLK CLKI2 MCLK Note MCLK may be a previously divided down version of CLKI, CLKI3, or BUSCLK. CPU To Memory Wait State Select Register REG[01Eh] n/a n/a n/a n/a n/a n/a CPU to Memory Wait State Select Bit 1 RW CPU to Memory Wait State Select Bit 0 bits 1-0 CPU to Memory Wait State Select Bits [1:0] These bits are used to optimize the handshaking between the host interface and the memory controller. The bits should be set according to the relationship between BCLK and MCLK (memory clock) Note BCLK can be either BUSCLK or BUSCLK / 2 depending on the setting of CONF5 (see Table 4-9, "Summary of Power-On/Reset Options," on page 33). Failure to meet the following conditions may lead to system crash which is recoverable only by RESET. Table 8-11 : Minimum Memory Timing Selection Wait State Bits [1:0] 00 01 10 11 Condition no restrictions 2 x period (MCLK) - 4ns > period(BCLK) period(MCLK) - 4ns > period(BCLK) Reserved Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 108 Epson Research and Development Vancouver Design Center 8.4.5 Memory Configuration Registers Memory Configuration Register REG[020h] SDRAM Init n/a n/a n/a n/a n/a n/a RW n/a bit 7 SDRAM Initialization This bit must be set to 1 before memory accesses are performed. Setting this bit to 1 after reset initializes the embedded SDRAM. Subsequent toggling of this bit after the first initialization has no effect. When the SDRAM Initialization bit is set, the actual initialization sequence occurs at the first SDRAM refresh cycle. The initialization sequence requires approximately 16 MCLKs to complete and memory accesses cannot be made while the initialization is in progress. Any concurrently issued memory access will occur after the completion of the initialization sequence. At least one SDRAM refresh period must happen before issuing any memory accesses. Note The default SDRAM refresh rate is based on the MCLK source frequency and is set using REG[21h] bits 2-0. If the refresh rate or MCLK rate is changed, the wait time will be different. Reset starts Reset ends Set SDRAM Init bit Initialization Sequence Starts Initialization Sequence Ends min 200s max 1 ref. period 16 Tmclk memory access allowed Figure 8-1: SDRAM Initialization Sequence S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 109 SDRAM Refresh Rate Register REG[021h] n/a Reserved n/a n/a n/a Reserved SDRAM Refresh Rate Bit 1 RW SDRAM Refresh Rate Bit 0 bit 6 bit 2 bits 1-0 Reserved. This bit must be set to 0. Reserved. This bit must be set to 0. SDRAM Refresh Rate Select Bits [2:0] These bits are set according to the MCLK source frequency (i.e., BUSCLK, CLKI, or CLKI3 as determined by REG[010h] bits 1-0). Table 8-12 : SDRAM Refresh Rate Selection SDRAM Refresh Rate Bits [1:0] 00 01 10 11 MCLK Source Frequency (MHz) 4.096 <= MClk < 8.192 8.192 <= MClk < 16.384 16.384 <= MClk < 32.768 32.768 <= MClk <= 50.000 SDRAM Timing Control Register 0 REG[02Ah] SDRAM Timing Control Bit 7 SDRAM Timing Control Bit 6 SDRAM Timing Control Bit 5 SDRAM Timing Control Bit 4 SDRAM Timing Control Bit 3 SDRAM Timing Control Bit 2 SDRAM Timing Control Bit 1 RW SDRAM Timing Control Bit 0 SDRAM Timing Control Register 1 REG[02Bh] n/a n/a n/a SDRAM SDRAM SDRAM Timing Timing Timing Control Bit 12 Control Bit 11 Control Bit 10 SDRAM Timing Control Bit 9 RW SDRAM Timing Control Bit 8 REG[02Ah] bits 7-0 REG[02Bh] bits 4-0 SDRAM Timing Control Bits [12:0] The SDRAM Timing Control registers must be set according to the frequency of MCLK as follows. Table 8-13 : SDRAM Timings Control Register Settings MCLK Source Frequency (MHz) 42 MCLK 50 33 MCLK < 42 MCLK < 33 REG[02Ah] 00h 00h 11h REG[02Bh] 01h 12h 13h Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 110 Epson Research and Development Vancouver Design Center 8.4.6 Panel Configuration Registers Panel Type Register REG[030h] EL Panel TFT 2x Data Mode Enable Format Select Panel Data Width Bit 1 Panel Data Width Bit 0 Panel Data Format Select Color/Mono. Panel Select Dual/Single Panel Select RW TFT/ Passive LCD Panel Select bit 7 EL Panel Mode Enable When this bit = 1, EL Panel support circuit is enabled. When this bit = 0, there is no hardware effect. This bit enables the S1D13806 built-in circuit for EL panels which require the Frame Rate Modulation (FRM) to remain static for one frame every 262143 frames (approximately 1 hour at 60Hz refresh). When this bit is enabled, the need for external circuitry to perform the above function is eliminated. TFT 2x Data Format Select For TFT/D-TFD only. When this bit = 1, the TFT 2x Data format is selected. When this bit = 0, the standard TFT Data format is selected. For details on the TFT 2x Data format, see Section 6.5.10, "TFT/D-TFD Panel Timing" on page 82. bit 6 bits 5-4 Panel Data Width Bits [1:0] These bits select passive LCD/TFT/D-TFD panel data width size. Table 8-14 : Panel Data Width Selection Panel Data Width Bits [1:0] 00 01 10 11 Passive LCD Panel Data Width 4-bit 8-bit 16-bit Reserved TFT/D-TFD Panel Data Width 1x Data Format 9-bit 12-bit 18-bit Reserved 2x Data Format 2 x 9-bit 2 x 12-bit Reserved Reserved bit 3 Panel Data Format Select When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. For AC timing see Section 6.5.5, "Single Color 8-Bit Panel Timing (Format 2)" on page 72. When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC timing see Section 6.5.4, "Single Color 8-Bit Panel Timing (Format 1)" on page 70. Color/Mono Panel Select When this bit = 1, color passive LCD panel is selected. When this bit = 0, monochrome passive LCD panel is selected. Dual/Single Panel Select When this bit = 1, dual passive LCD panel is selected. When this bit = 0, single passive LCD panel is selected. bit 2 bit 1 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 111 bit 0 TFT/Passive LCD Panel Select When this bit = 1, TFT/D-TFD panel is selected. When this bit = 0, passive LCD panel is selected. MOD Rate Register REG[031h] n/a n/a RW MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit 5 4 3 2 1 0 bits 5-0 MOD Rate Bits [5:0] For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal (DRDY). When these bits are all 0's the MOD output signal toggles every FPFRAME. These bits are for passive LCD panels only. LCD Horizontal Display Width Register REG[032h] n/a RW LCD LCD LCD LCD LCD LCD LCD Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 6-0 LCD Horizontal Display Width Bits [6:0] These bits specify the LCD panel horizontal display width, in 8 pixel resolution. Horizontal display width in number of pixels = ((ContentsOfThisRegister)+ 1) x 8 The Horizontal Display Width has certain limitations on the values that may be used for each type of LCD panel. Use of values that do not meet the limitations listed in the following table result in undefined behavior. Table 8-15: Horizontal Display Width (Pixels) Panel Type Passive Single Passive Dual TFT Horizontal Display Width (Pixels) must be divisible by 16 must be divisible by 32 must be divisible by 8 Note This register must be programmed such that REG[032h] 3 (32 pixels). Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 112 Epson Research and Development Vancouver Design Center LCD Horizontal Non-Display Period Register REG[034h] n/a n/a n/a LCD Horizontal Non-Display Period Bit 4 LCD Horizontal Non-Display Period Bit 3 LCD Horizontal Non-Display Period Bit 2 LCD Horizontal Non-Display Period Bit 1 RW LCD Horizontal Non-Display Period Bit 0 bits 4-0 LCD Horizontal Non-Display Period Bits [4:0] These bits specify the LCD panel HNDP width in 8 pixel resolution. HNDP width in number of pixels = ((ContentsOfThisRegister) + 1) x 8 Note This register must be programmed such that REG[034h] 3 (32 pixels). Note For TFT/D-TFD only: REG[034h] + 1 (REG[035h] + 1) + (REG[036h] bits 3-0 + 1) TFT FPLINE Start Position Register REG[035h] n/a n/a n/a TFT FPLINE Start Position Bit 4 TFT FPLINE Start Position Bit 3 TFT FPLINE Start Position Bit 2 TFT FPLINE Start Position Bit 1 RW TFT FPLINE Start Position Bit 0 bits 4-0 TFT FPLINE Start Position Bits [4:0] For TFT/D-TFD panels only, these bits specify the delay, in 8 pixel resolution, from the start of the horizontal non-display period to the leading edge of the FPLINE pulse. For TFT 1x Data Format at 4/8 bpp color depth: FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 5] For TFT 1x Data Format at 16 bpp color depth: FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 6] For TFT 2x Data Format at 4/8 bpp color depth: FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 4] For TFT 2x Data Format at 16 bpp color depth: FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 5] Note REG[034h] + 1 (REG[035h] + 1) + (REG[036h] bits 3-0 + 1) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 113 TFT FPLINE Pulse Width Register REG[036h] LCD FPLINE Polarity Select n/a n/a n/a TFT FPLINE Pulse Width Bit 3 TFT FPLINE Pulse Width Bit 2 TFT FPLINE Pulse Width Bit 1 RW TFT FPLINE Pulse Width Bit 0 bit 7 LCD FPLINE Polarity Select This bit selects the polarity of FPLINE for all LCD panels. When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for passive LCD. When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for passive LCD. Table 8-16 : LCD FPLINE Polarity Selection LCD FPLINE Polarity Select 0 1 Passive LCD FPLINE Polarity active high active low TFT FPLINE Polarity active low active high bits 3-0 TFT FPLINE Pulse Width Bits [3:0] For TFT/D-TFD panels only, these bits specify the pulse width of the FPLINE output signal in 8 pixel resolution. FPLINE pulse width in number of pixels = ((ContentsOfThisRegister) + 1) x 8 The maximum FPLINE pulse width is 128 pixels. Note REG[034h] + 1 (REG[035h] + 1) + (REG[036h] bits 3-0 + 1) LCD Vertical Display Height Register 0 REG[038h] LCD Vertical Display Height Bit 7 LCD Vertical Display Height Bit 6 LCD Vertical Display Height Bit 5 LCD Vertical Display Height Bit 4 LCD Vertical Display Height Bit 3 LCD Vertical Display Height Bit 2 LCD Vertical Display Height Bit 1 RW LCD Vertical Display Height Bit 0 LCD Vertical Display Height Register 1 REG[039h] n/a n/a n/a n/a n/a n/a LCD Vertical Display Height Bit 9 RW LCD Vertical Display Height Bit 8 REG[038h] bits 7-0 REG[039h] bits 1-0 LCD Vertical Display Height Bits [9:0] These bits specify the LCD panel vertical display height, in 1 line resolution. Vertical display height in number of lines = (ContentsOfThisRegister) + 1 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 114 Epson Research and Development Vancouver Design Center LCD Vertical Non-Display Period Register REG[03Ah] LCD Vertical Non-Display Period Status (RO) n/a LCD Vertical Non-Display Period Bit 5 LCD Vertical Non-Display Period Bit 4 LCD Vertical Non-Display Period Bit 3 LCD Vertical Non-Display Period Bit 2 LCD Vertical Non-Display Period Bit 1 RW LCD Vertical Non-Display Period Bit 0 bit 7 LCD Vertical Non-Display Period Status This is a read-only status bit. When a read from this bit = 1, a LCD panel vertical non-display period is occurring. When a read from this bit = 0, the LCD panel output is in a vertical display period. LCD Vertical Non-Display Period Bits [5:0] These bits specify the LCD panel vertical non-display period height in 1 line resolution. Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1 Note bits 5-0 For TFT/D-TFD only: (REG[03Ah] bits 5-0 + 1) (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1) TFT FPFRAME Start Position Register REG[03Bh] n/a n/a TFT FPFRAME Start Position Bit 5 TFT FPFRAME Start Position Bit 4 TFT FPFRAME Start Position Bit 3 TFT FPFRAME Start Position Bit 2 TFT FPFRAME Start Position Bit 1 RW TFT FPFRAME Start Position Bit 0 bits 5-0 TFT FPFRAME Start Position Bits [5:0] For TFT/D-TFD panels only, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the FPFRAME pulse. FPFRAME start position in number of lines = (ContentsOfThisRegister) + 1 Note (REG[03Ah] bits 5-0 + 1) (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 115 TFT FPFRAME Pulse Width Register REG[03Ch] LCD FPFRAME Polarity Select n/a n/a n/a n/a TFT FPFRAME Pulse Width Bit 2 TFT FPFRAME Pulse Width Bit 1 RW TFT FPFRAME Pulse Width Bit 0 bit 7 LCD FPFRAME Polarity Select This bit selects the polarity of FPFRAME for all LCD panels. When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for passive LCD. When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for passive LCD. Table 8-17 : LCD FPFRAME Polarity Selection LCD FPFRAME Polarity Select 0 1 Passive LCD FPFRAME Polarity active high active low TFT FPFRAME Polarity active low active high bits 2-0 TFT FPFRAME Pulse Width Bits [2:0] For TFT/D-TFD panels only, these bits specify the pulse width of the FPFRAME output signal in number of lines. FPFRAME pulse width in number of lines = (ContentsOfThisRegister) + 1 Note (REG[03Ah] bits 5-0 + 1) (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1) 8.4.7 LCD Display Mode Registers LCD Display Mode Register REG[040h] LCD Display Blank n/a n/a SwivelView Enable Bit 1 n/a LCD Bit-perpixel Select Bit 2 LCD Bit-perpixel Select Bit 1 RW LCD Bit-perpixel Select Bit 0 bit 7 LCD Display Blank When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are forced to zero (i.e. the screen is blanked). When this bit = 0, the LCD display pipeline is enabled. Note If a dual panel is used, the Dual Panel Buffer (REG[041h] bit 0) must be disabled (set to 1) before blanking the LCD display. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 116 Epson Research and Development Vancouver Design Center bit 4 SwivelView Enable Bit 1 When this bit = 1, the LCD display image is rotated 180 clockwise. Please refer to Section 15, "SwivelViewTM" on page 177 for application and limitations. When this bit = 0, there is no hardware effect. This bit in conjunction with SwivelViewTM Enable Bit 0 achieves the following hardware rotations. Table 8-18: Setting SwivelView Modes SwivelView Enable Bits SwivelView Enable Bit 0 (REG[1FCh] bit 6) SwivelView Enable Bit 1 (REG[040h] bit 4) SwivelViewTM Modes Normal 0 0 SwivelView 90 1 0 SwivelView 180 0 1 SwivelView 270 1 1 bits 2-0 LCD Bit-per-pixel Select Bits [2:0] These bits select the color depth (bit-per-pixel) for the displayed data. Note 16 bpp color depth bypasses the LUT and supports up to 64K colors (4096 colors if dithering disabled, see REG[041h] bit 1). TFT/D-TFD panels support up to 64K colors. Table 8-19 : LCD Bit-per-pixel Selection Bit-per-pixel Select Bits [1:0] 000-001 010 011 100 101 110-111 Color Depth (bpp) Reserved 4 bpp 8 bpp Reserved 16 bpp Reserved S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 117 LCD Miscellaneous Register REG[041h] n/a n/a n/a n/a n/a n/a Dithering Disable RW Dual Panel Buffer Disable bit 1 Dithering Disable When this bit = 0, dithering on the passive LCD panel for 16 bpp mode is enabled allowing a maximum of 64K colors (216) or 64 gray shades. When this bit = 1, dithering on the passive LCD panel for 16 bpp mode is disabled, allowing a maximum of 4096 colors (212) or 16 gray shades. The dithering algorithm provides more shades of each primary color when in 16 bpp mode. This bit has no effect in 4/8 bpp modes where dithering is not supported. All passive STN color panels are controlled using 3 bits for each pixel (RGB) for a total of 8 possible colors. LCD controllers use a combination of Frame Rate Modulation (FRM) and dithering to achieve more than 8 colors per pixel. FRM can achieve 16 shades of color for each RGB component resulting in a total of 4096 possible colors (16x16x16). Dithering uses a 4 pixel square formation and applies a set of 4 hard-coded patterns for each of the 16 shades of color. This expands the original 16 shades of color from the FRM logic to 64 shades per RGB component which results in 256K colors per pixel (64x64x64). For the S1D13806, 16 bpp is arranged as 5-6-5 RGB. In this mode, when dithering is enabled, the LUT is bypassed and the original 16-bit data is used as a pointer into the 64 shades per color in the following manner. (5-6-5 RGB) 32 possible Red, 64 possible Green, 32 possible Blue This combination of FRM and dithering results in 256K colors/pixel, however, the 16 bpp limitation of the S1D13806 limits this to 64K colors/pixel. bit 0 Dual Panel Buffer Disable This bit is used to disable the dual panel buffer. When this bit = 1, the dual panel buffer is disabled. When this bit = 0, the dual panel buffer is enabled. When a single panel is selected, the dual panel buffer is automatically disabled and this bit has no effect. Note The dual panel buffer is needed to fully support dual panels. Disabling the dual panel buffer may allow higher resolution/color display modes than would otherwise be possible. However, disabling the dual panel buffer reduces image contrast and overall display quality. For details on Frame Rate Calculation, see Section 18, "Clocking" on page 189. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 118 Epson Research and Development Vancouver Design Center LCD Display Start Address Register 0 REG[042h] LCD Display Start Address Bit 7 LCD Display Start Address Bit 6 LCD Display Start Address Bit 5 LCD Display Start Address Bit 4 LCD Display Start Address Bit 3 LCD Display Start Address Bit 2 LCD Display Start Address Bit 1 RW LCD Display Start Address Bit 0 LCD Display Start Address Register 1 REG[043h] LCD Display Start Address Bit 15 LCD Display Start Address Bit 14 LCD Display Start Address Bit 13 LCD Display Start Address Bit 12 LCD Display Start Address Bit 11 LCD Display Start Address Bit 10 LCD Display Start Address Bit 9 RW LCD Display Start Address Bit 8 LCD Display Start Address Register 2 REG[044h] n/a n/a n/a n/a LCD Display Start Address Bit 19 LCD Display Start Address Bit 18 LCD Display Start Address Bit 17 RW LCD Display Start Address Bit 16 REG[042h] bits 7-0 REG[043h] bits 7-0 REG[044h] bits 3-0 LCD Display Start Address Bits [19:0] This register forms the 20-bit address of the starting word of the LCD image in the display buffer. This is a word address. An entry of 0 0000h into these registers represents the first word of the display buffer, an entry of 0 0001h represents the second word of the display buffer, and so on. LCD Memory Address Offset Register 0 REG[046h] LCD Memory Address Offset Bit 7 LCD Memory Address Offset Bit 6 LCD Memory Address Offset Bit 5 LCD Memory Address Offset Bit 4 LCD Memory Address Offset Bit 3 LCD Memory Address Offset Bit 2 LCD Memory Address Offset Bit 1 RW LCD Memory Address Offset Bit 0 LCD Memory Address Offset Register 1 REG[047h] n/a n/a n/a n/a n/a LCD Memory Address Offset Bit 10 LCD Memory Address Offset Bit 9 RW LCD Memory Address Offset Bit 8 REG[046h] bits 7-0 REG[047h] bits 2-0 LCD Memory Address Offset Bits [10:0] These bits are the LCD display's 11-bit address offset from the starting word of line "n" to the starting word of line "n + 1". A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 119 LCD Pixel Panning Register REG[048h] n/a n/a n/a n/a n/a n/a LCD Pixel Panning Bit 1 RW LCD Pixel Panning Bit 0 bits 1-0 LCD Pixel Panning Bits [1:0] This register is used to control the horizontal pixel panning of the LCD display. The display can be panned to the left by programming its respective Pixel Panning Bits to a nonzero value. This value represents the number of pixels panned. The maximum pan value is dependent on the display mode as shown in the table below. Table 8-20 : LCD Pixel Panning Selection Color Depth (bpp) 4 bpp 8 bpp 16 bpp Screen 2 Pixel Panning Bits Used Bits [1:0] Bit 0 --- Note Smooth horizontal panning can be achieved by a combination of this register and the LCD Display Start Address registers (REG[042h], REG[043h], REG[044h]). LCD Display FIFO High Threshold Control Register REG[04Ah] n/a n/a LCD Display FIFO High Threshold Bit 5 LCD Display FIFO High Threshold Bit 4 LCD Display FIFO High Threshold Bit 3 LCD Display FIFO High Threshold Bit 2 LCD Display FIFO High Threshold Bit 1 RW LCD Display FIFO High Threshold Bit 0 bits 5-0 LCD Display FIFO High Threshold Bits [5:0] These bits are used to optimize the display memory request arbitration. When this register is set to 00h, the threshold is automatically set in hardware. However, programming may be required if screen corruption is present (see Section 18.2, "Example Frame Rates" on page 192). Note This register does not need to be used in single display modes and may only be required in some display modes where two displays are active (see Section 16.3, "Bandwidth Limitation" on page 187). Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 120 Epson Research and Development Vancouver Design Center ) LCD Display FIFO Low Threshold Control Register REG[04Bh] n/a n/a LCD Display FIFO Low Threshold Bit 5 LCD Display FIFO Low Threshold Bit 4 LCD Display FIFO Low Threshold Bit 3 LCD Display FIFO Low Threshold Bit 2 LCD Display FIFO Low Threshold Bit 1 RW LCD Display FIFO Low Threshold Bit 0 its 5-0 LCD Display FIFO Low Threshold Bits [5:0] When this register is set to 00h, the threshold is automatically set in hardware. If it becomes necessary to adjust REG[04Ah] from its default value, then the following formula must be maintained: REG[04Bh] REG[04Ah] and REG[04Bh] 3Ch 8.4.8 CRT/TV Configuration Registers CRT/TV Horizontal Display Width Register REG[050h] n/a RW CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bits 6-0 CRT/TV Horizontal Display Width Bits [6:0] These bits specify the CRT/TV horizontal display width, in 8 pixel resolution. Horizontal display width in number of pixels = ((ContentsOfThisRegister) + 1) x 8 CRT/TV Horizontal Non-Display Period Register REG[052h] n/a n/a CRT/TV Horizontal Non-Display Period Bit 5 CRT/TV Horizontal Non-Display Period Bit 4 CRT/TV Horizontal Non-Display Period Bit 3 CRT/TV Horizontal Non-Display Period Bit 2 CRT/TV Horizontal Non-Display Period Bit 1 RW CRT/TV Horizontal Non-Display Period Bit 0 bits 5-0 CRT/TV Horizontal Non-Display Period Bits [5:0] These bits specify the CRT/TV horizontal non-display period width in 8 pixel resolution. Horizontal non-display period width in number of pixels = ((ContentsOfThisRegister) + 1) x 8 for CRT mode (ContentsOfThisRegister) x 8 + 6 for TV mode with NTSC output (ContentsOfThisRegister) x 8 + 7 for TV mode with PAL output Note For CRT, the recommended minimum value which should be programmed into this register is 3 (32 pixels). Note REG[052h] + 1 (REG[053h] + 1) + (REG[054h] bits 3-0 + 1) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 121 CRT/TV HRTC Start Position Register REG[053h] n/a n/a CRT/TV HRTC Start Position Bit 5 CRT/TV HRTC Start Position Bit 4 CRT/TV HRTC Start Position Bit 3 CRT/TV HRTC Start Position Bit 2 CRT/TV HRTC Start Position Bit 1 RW CRT/TV HRTC Start Position Bit 0 bits 5-0 CRT/TV HRTC Start Position Bits [5:0] For CRT/TV, these bits specify the delay, in 8 pixel resolution, from the start of the horizontal non-display period to the leading edge of the HRTC pulse. The following equations can be used to determine the HRTC start position in number of pixels for each display type: HRTC start position in number of pixels=: [(ContentsOfThisRegister) x 8 + 4] for CRT with 4/8 bpp color depth [(ContentsOfThisRegister) x 8 + 5] for CRT in 16 bpp color depth [((ContentsOfThisRegister) + 1) x 8 - 7] for TV-NTSC in 4/8 bpp color depth [((ContentsOfThisRegister) + 1) x 8 - 5] for TV-NTSC in 16 bpp color depth [((ContentsOfThisRegister) + 1) x 8 - 7] for TV-PAL in 4/8 bpp color depth [((ContentsOfThisRegister) + 1) x 8 - 5] for TV-PAL in 16 bpp color depth Note REG[052h] + 1 (REG[053h] + 1) + (REG[054h] bits 3-0 + 1) CRT/TV HRTC Pulse Width Register REG[054h] CRT HRTC Polarity Select n/a n/a n/a CRT HRTC Pulse Width Bit 3 CRT HRTC Pulse Width Bit 2 CRT HRTC Pulse Width Bit 1 RW CRT HRTC Pulse Width Bit 0 bit 7 CRT HRTC Polarity Select This bit selects the polarity of HRTC for CRTs. When this bit = 1, the HRTC pulse is active high. When this bit = 0, the HRTC pulse is active low. Note For TV, this bit must be set to 0. bits 3-0 CRT HRTC Pulse Width Bits [3:0] These bits specify the pulse width of the CRT HRTC output signal in 8 pixel resolution. HRTC pulse width in number of pixels = ((ContentsOfThisRegister) + 1) x 8 Note For TV, these bits must be set to 0. Note REG[052h] + 1 (REG[053h] + 1) + (REG[054h] bits 3-0 + 1) Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 122 Epson Research and Development Vancouver Design Center CRT/TV Vertical Display Height Register 0 REG[056h] CRT/TV Vertical Display Height Bit 7 CRT/TV Vertical Display Height Bit 6 CRT/TV Vertical Display Height Bit 5 CRT/TV Vertical Display Height Bit 4 CRT/TV Vertical Display Height Bit 3 CRT/TV Vertical Display Height Bit 2 CRT/TV Vertical Display Height Bit 1 RW CRT/TV Vertical Display Height Bit 0 CRT/TV Vertical Display Height Register 1 REG[057h] n/a n/a n/a n/a n/a n/a CRT/TV Vertical Display Height Bit 9 RW CRT/TV Vertical Display Height Bit 8 REG[056h] bits 7-0 REG[057h] bits 1-0 CRT/TV Vertical Display Height Bits [9:0] These bits specify the CRT/TV vertical display height, in 1 line resolution. Vertical display height in number of lines = (ContentsOfThisRegister) + 1 CRT/TV Vertical Non-Display Period Register REG[058h] CRT/TV Vertical NonDisplay Period Status (RO) CRT/TV Vertical NonDisplay Period Bit 6 CRT/TV Vertical NonDisplay Period Bit 5 CRT/TV Vertical NonDisplay Period Bit 4 CRT/TV Vertical NonDisplay Period Bit 3 CRT/TV Vertical NonDisplay Period Bit 2 CRT/TV Vertical NonDisplay Period Bit 1 RW CRT/TV Vertical NonDisplay Period Bit 0 bit 7 CRT/TV Vertical Non-Display Period Status This is a read-only status bit. When a read from this bit = 1, a CRT/TV vertical non-display period is occurring. When a read from this bit = 0, the CRT/TV output is in a vertical display period. CRT/TV Vertical Non-Display Period Bits [6:0] These bits specify the CRT/TV vertical non-display period height in 1 line resolution. Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1 Note bits 6-0 (REG[058h] bits 6-0 + 1) (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 123 CRT/TV VRTC Start Position Register REG[059h] n/a CRT/TV VRTC Start Position Bit 6 CRT/TV VRTC Start Position Bit 5 CRT/TV VRTC Start Position Bit 4 CRT/TV VRTC Start Position Bit 3 CRT/TV VRTC Start Position Bit 2 CRT/TV VRTC Start Position Bit 1 RW CRT/TV VRTC Start Position Bit 0 bits 6-0 CRT/TV VRTC Start Position Bits [6:0] For CRT/TV, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the VRTC pulse. VRTC start position in number of lines = (ContentsOfThisRegister) + 1 Note (REG[058h] bits 6-0 + 1) (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1) CRT VRTC Pulse Width Register REG[05Ah] CRT VRTC Polarity Select n/a n/a n/a n/a CRT VRTC Pulse Width Bit 2 CRT VRTC Pulse Width Bit 1 RW CRT VRTC Pulse Width Bit 0 bit 7 CRT VRTC Polarity Select This bit selects the polarity of VRTC for CRT. When this bit = 1, the VRTC pulse is active high. When this bit = 0, the VRTC pulse is active low. Note For TV, this bit must be set to 0. bits 2-0 CRT VRTC Pulse Width Bits [2:0] These bits specify the pulse width of the CRT VRTC output signal in number of lines. VRTC pulse width in number of lines = (ContentsOfThisRegister) + 1 Note For TV, these bits must be set to 0. Note (REG[058h] bits 6-0 + 1) (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1) Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 124 Epson Research and Development Vancouver Design Center TV Output Control Register REG[05Bh] n/a n/a TV Chrominance Filter Enable TV Luminance Filter Enable DAC Output Level Select n/a RW TV S-Video/ TV Composite PAL/NTSC Output Select Output Select bit 5 TV Chrominance Filter Enable When this bit = 1, the TV chrominance filter is enabled. When this bit = 0, the TV chrominance filter is disabled. The chrominance filter adjusts the color of the TV by limiting the bandwidth of the chrominance signal (reducing cross-luminance distortion). This reduces the "ragged edges" seen at boundaries between sharp color transitions. This filter is most useful for composite video output. TV Luminance Filter Enable When this bit = 1, the TV luminance filter is enabled. When this bit = 0, the TV luminance filter is disabled. The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the luminance signal (reducing cross-chrominance distortion). This reduces the "rainbowlike" colors at boundaries between sharp luminance transitions. This filter is most useful for composite video output. DAC Output Level Select When this bit is set to 1 it allows IREF to be reduced. This bit should be set as described in the following table. Table 8-21: DAC Output Level Selection LCD Enabled x x x CRT Disabled Enabled Enabled = don't care TV Disabled Disabled Enabled REG[05Bh] bit 3 x 1 0 IREF (mA) x 4.6 9.2 bit 4 bit 3 Note Figure 4-3: "External Circuitry for CRT Interface" on page 36 shows an example implementation of the required external CRT/TV IREF circuitry. bit 1 TV S-Video/Composite Output Select When this bit = 1, S-Video TV signal output is selected. When this bit = 0, Composite TV signal output is selected. TV PAL/NTSC Output Select When this bit = 1, PAL format TV signal output is selected. When this bit = 0, NTSC format TV signal output is selected. This bit must be set to 0 when CRT is enabled. bit 0 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 125 8.4.9 CRT/TV Display Mode Registers CRT/TV Display Mode Register REG[060h] CRT/TV Display Blank n/a n/a n/a n/a CRT/TV Bitper-pixel Select Bit 2 CRT/TV Bitper-pixel Select Bit 1 RW CRT/TV Bitper-pixel Select Bit 0 bit 7 CRT/TV Display Blank When this bit = 1 the CRT/TV display pipeline is disabled and all CRT/TV data outputs are forced to zero (the screen is blanked). When this bit = 0 the CRT display pipeline is enabled. CRT/TV Bit-per-pixel Select Bits [2:0] These bits select the bit-per-pixel for the displayed data. Note bits 2-0 Color depth of 16 bpp bypasses the LUT and support up to 64K colors on the CRT/TV. . Table 8-22 : CRT/TV Bit-per-pixel Selection Bit-per-pixel Select Bits 1:0 000 001 010 011 100 101 110-111 Color Depth (bpp) Reserved Reserved 4 bpp 8 bpp Reserved 16 bpp Reserved Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 126 Epson Research and Development Vancouver Design Center CRT/TV Display Start Address Register 0 REG[062h] CRT/TV Display Start Address Bit 7 CRT/TV Display Start Address Bit 6 CRT/TV Display Start Address Bit 5 CRT/TV Display Start Address Bit 4 CRT/TV Display Start Address Bit 3 CRT/TV Display Start Address Bit 2 CRT/TV Display Start Address Bit 1 RW CRT/TV Display Start Address Bit 0 CRT/TV Display Start Address Register 1 REG[063h] CRT/TV Display Start Address Bit 15 CRT/TV Display Start Address Bit 14 CRT/TV Display Start Address Bit 13 CRT/TV Display Start Address Bit 12 CRT/TV Display Start Address Bit 11 CRT/TV Display Start Address Bit 10 CRT/TV Display Start Address Bit 9 RW CRT/TV Display Start Address Bit 8 CRT/TV Display Start Address Register 2 REG[064h] n/a n/a n/a n/a CRT/TV Display Start Address Bit 19 CRT/TV Display Start Address Bit 18 CRT/TV Display Start Address Bit 17 RW CRT/TV Display Start Address Bit 16 REG[062h] bits 7-0 REG[063h] bits 7-0 REG[064h] bits 3-0 CRT/TV Start Address Bits [19:0] This register forms the 20-bit address for the starting word of the CRT/TV image in the display buffer. This is a word address. An entry of 00000h into these registers represents the first word of the display buffer, an entry of 00001h represents the second word of the display buffer, and so on. CRT/TV Memory Address Offset Register 0 REG[066h] CRT/TV Memory Address Offset Bit 7 CRT/TV Memory Address Offset Bit 6 CRT/TV Memory Address Offset Bit 5 CRT/TV Memory Address Offset Bit 4 CRT/TV Memory Address Offset Bit 3 CRT/TV Memory Address Offset Bit 2 CRT/TV Memory Address Offset Bit 1 RW CRT/TV Memory Address Offset Bit 0 CRT/TV Memory Address Offset Register 1 REG[067h] n/a n/a n/a n/a n/a CRT/TV Memory Address Offset Bit 10 CRT/TV Memory Address Offset Bit 9 RW CRT/TV Memory Address Offset Bit 8 REG[066h] bits 7-0 REG[067h] bits 2-0 CRT/TV Memory Address Offset Bits [10:0] These bits are the CRT/TV display's 11-bit address offset from the starting word of line "n" to the starting word of line "n + 1". A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 127 CRT/TV Pixel Panning Register REG[068h] n/a n/a n/a n/a n/a n/a CRT/TV Pixel Panning Bit 1 RW CRT/TV Pixel Panning Bit 0 bits 1-0 CRT/TV Pixel Panning Bits [1:0] This register is used to control the horizontal pixel panning of the CRT/TV display. The display can be panned to the left by programming its respective Pixel Panning Bits to a non-zero value. This value represents the number of pixels panned. The maximum pan value is dependent on the display mode as shown in the table below. Table 8-23 : CRT/TV Pixel Panning Selection Color Depth (bpp) 4 bpp 8 bpp 16 bpp Screen 2 Pixel Panning Bits Used Bits [1:0] Bit 0 --- Note Smooth horizontal panning can be achieved by a combination of this register and the CRT/TV Display Start Address registers (REG[062h], REG[063h], REG[064h]). CRT/TV Display FIFO High Threshold Control Register REG[06Ah] CRT/TV Display FIFO High Threshold Bit 5 CRT/TV Display FIFO High Threshold Bit 4 CRT/TV Display FIFO High Threshold Bit 3 CRT/TV Display FIFO High Threshold Bit 2 CRT/TV Display FIFO High Threshold Bit 1 RW CRT/TV Display FIFO High Threshold Bit 0 n/a n/a bits 5-0 CRT/TV Display FIFO High Threshold Bits [5:0] These bits are used to optimize the display memory request arbitration. When this register is set to 00h, the threshold is automatically set in hardware. However, programming may be required if screen corruption is present (see Section 18.2, "Example Frame Rates" on page 192). Note This register does not need to be used in single display modes and may only be required in some display modes where two displays are active (see Section 16.3, "Bandwidth Limitation" on page 187). Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 128 Epson Research and Development Vancouver Design Center CRT/TV Display FIFO Low Threshold Control Register REG[06Bh] CRT/TV Display FIFO Low Threshold Bit 5 CRT/TV Display FIFO Low Threshold Bit 4 CRT/TV Display FIFO Low Threshold Bit 3 CRT/TV Display FIFO Low Threshold Bit 2 CRT/TV Display FIFO Low Threshold Bit 1 RW CRT/TV Display FIFO Low Threshold Bit 0 n/a n/a bits 5-0 CRT/TV Display FIFO Low Threshold Bits [5:0] When this register is set to 00h, the threshold is automatically set in hardware. If it becomes necessary to adjust REG[06Ah] from its default value, then the following formula must be maintained. REG[06Bh] REG[06Ah] and REG[06Bh] 3Ch 8.4.10 LCD Ink/Cursor Registers LCD Ink/Cursor Control Register REG[070h] n/a n/a n/a n/a n/a n/a LCD Ink/Cursor Mode Bit 1 RW LCD Ink/Cursor Mode Bit 0 bits 1-0 LCD Ink/Cursor Control Bits [1:0] These bits enable the LCD Ink/Cursor circuitry. Table 8-24 : LCD Ink/Cursor Selection LCD Ink/Cursor Bits [1:0] 00 01 10 11 Mode Inactive Cursor Ink Reserved Note While in Ink mode, the Cursor X and Y Position registers must be set to 00h. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 129 LCD Ink/Cursor Start Address Register REG[071h] RW LCD LCD LCD LCD LCD LCD LCD LCD Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 7-0 LCD Ink/Cursor Start Address Bits [7:0] Encoded bits defining the start address for the LCD Ink/Cursor. For Cursor modes, a start address of 0 should be valid for most applications. For Ink or special Cursor modes, the start address should be set at an address location that does not conflict with the display memory of dual panel buffer, which always takes the top M memory locations in bytes. M = (Panel Height x Panel Width / 16) x c where c = 1 for monochrome panel = 4 for color panel Table 8-25 : LCD Ink/Cursor Start Address Encoding LCD Ink/Cursor Start Address Bits [7:0] 0 n = 160...1 n = 255...161 Start Address Memory Size - 1024 Memory Size - n x 8192 invalid Note The effect of this register takes place at the next LCD vertical non-display period. Note See Section 10, "Display Buffer" on page 157 for display buffer organization. LCD Cursor X Position Register 0 REG[072h] RW LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X Position Position Position Position Position Position Position Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD Cursor X Position Register 1 REG[073h] LCD Cursor X Sign n/a n/a n/a n/a n/a RW LCD Cursor X LCD Cursor X Position Position Bit 9 Bit 8 REG[073h] bit 7 LCD Cursor X Sign When this bit = 1, it defines the LCD Cursor X Position register to be a negative number. The negative number shall not exceed 63 decimal. When this bit = 0, it defines the LCD Cursor X Position register to be a positive number. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 130 Epson Research and Development Vancouver Design Center REG[072h] bits 7-0 REG[073h] bits 1-0 LCD Cursor X Position Bits [9:0] A 10-bit register that defines the horizontal position of the LCD Cursor's top left hand corner in pixel units. This register is only valid when Cursor has been selected in the LCD Ink/Cursor select registers. Note The effect of REG[072h] through REG[074h] takes place only after REG[075h] is written and at the next LCD vertical non-display period.The effect of REG[075h] takes place at the next LCD vertical non-display period. LCD Cursor Y Position Register 0 REG[074h] RW LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y Position Position Position Position Position Position Position Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD Cursor Y Position Register 1 REG[075h] LCD Cursor Y Sign n/a n/a n/a n/a n/a RW LCD Cursor Y LCD Cursor Y Position Position Bit 9 Bit 8 REG[075h] bit 7 LCD Cursor Y Sign When this bit = 1, it defines the LCD Cursor Y Position register to be a negative number. The negative number shall not exceed 63 decimal. When this bit = 0, it defines the LCD Cursor Y Position register to be a positive number. LCD Cursor Y Position Bits [9:0] A 10-bit register that defines the vertical position of the LCD Cursor's top left hand corner in pixel units. This register is only valid when Cursor has been selected in the LCD Ink/Cursor select registers. Note REG[074h] bits 7-0 REG[075h] bits 1-0 The effect of REG[072h] through REG[074h] takes place only after REG[075h] is written and at the next LCD vertical non-display period.The effect of REG[075h] takes place at the next LCD vertical non-display period. LCD Ink/Cursor Blue Color 0 Register REG[076h] n/a n/a n/a LCD Ink/Cursor Blue Color 0 Bit 4 LCD Ink/Cursor Blue Color 0 Bit 3 LCD Ink/Cursor Blue Color 0 Bit 2 LCD Ink/Cursor Blue Color 0 Bit 1 RW LCD Ink/Cursor Blue Color 0 Bit 0 bits 4-0 LCD Ink/Cursor Blue Color 0 Bits[4:0] These bits define the blue LCD Ink/Cursor color 0. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 131 LCD Ink/Cursor Green Color 0 Register REG[077h] n/a n/a RW LCD LCD LCD LCD LCD LCD Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5-0 LCD Ink/Cursor Green Color 0 Bits[5:0] These bits define the green LCD ink/Cursor color 0. LCD Ink/Cursor Red Color 0 Register REG[078h] n/a n/a n/a LCD Ink/Cursor Red Color 0 Bit 4 LCD Ink/Cursor Red Color 0 Bit 3 LCD Ink/Cursor Red Color 0 Bit 2 LCD Ink/Cursor Red Color 0 Bit 1 RW LCD Ink/Cursor Red Color 0 Bit 0 bits 4-0 LCD Ink/Cursor Red Color 0 Bits[4:0] These bits define the red LCD Ink/Cursor color 0. LCD Ink/Cursor Blue Color 1 Register REG[07Ah] n/a n/a n/a LCD Ink/Cursor Blue Color 1 Bit 4 LCD Ink/Cursor Blue Color 1 Bit 3 LCD Ink/Cursor Blue Color 1 Bit 2 LCD Ink/Cursor Blue Color 1 Bit 1 RW LCD Ink/Cursor Blue Color 1 Bit 0 bits 4-0 LCD Ink/Cursor Blue Color 1 Bits[4:0] These bits define the blue LCD Ink/Cursor color 1. LCD Ink/Cursor Green Color 1 Register REG[07Bh] n/a n/a RW LCD LCD LCD LCD LCD LCD Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5-0 LCD Ink/Cursor Green Color 1 Bits[5:0] These bits define the green LCD Ink/Cursor color 1. LCD Ink/Cursor Red Color 1 Register REG[07Ch] n/a n/a n/a LCD Ink/Cursor Red Color 1 Bit 4 LCD Ink/Cursor Red Color 1 Bit 3 LCD Ink/Cursor Red Color 1 Bit 2 LCD Ink/Cursor Red Color 1 Bit 1 RW LCD Ink/Cursor Red Color 1 Bit 0 bits 4-0 LCD Ink/Cursor Red Color 1 Bits[4:0] These bits define the red LCD Ink/Cursor color 1. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 132 Epson Research and Development Vancouver Design Center LCD Ink/Cursor FIFO High Threshold Register REG[07Eh] LCD Ink/Cursor FIFO High Threshold Bit 3 LCD Ink/Cursor FIFO High Threshold Bit 2 LCD Ink/Cursor FIFO High Threshold Bit 1 RW LCD Ink/Cursor FIFO High Threshold Bit 0 n/a n/a n/a n/a bits 3-0 LCD Ink/Cursor FIFO High Threshold Bits [3:0] These bits are used to optimize the display memory request arbitration for the Hardware Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in hardware. 8.4.11 CRT/TV Ink/Cursor Registers CRT/TV Ink/Cursor Control Register REG[080h] n/a n/a n/a n/a n/a n/a CRT/TV Ink/Cursor Mode Bit 1 RW CRT/TV Ink/Cursor Mode Bit 0 bits 1-0 CRT/TV Ink/Cursor Control Bits [1:0] These bits enable the CRT/TV Ink/Cursor circuitry. Table 8-26 : CRT/TV Ink/Cursor Selection CRT/TV Ink/Cursor Bits [1:0] 00 01 10 11 Mode Inactive Cursor Ink Reserved Note While in Ink mode, the Cursor X and Y Position registers must be set to 00h. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 133 CRT/TV Ink/Cursor Start Address Register REG[081h] RW CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 7-0 CRT/TV Ink/Cursor Start Address Bits [7:0] Encoded bits defining the start address for the CRT/TV Ink/Cursor. For Cursor modes, a start address of 0 should be valid for most applications. For Ink or special Cursor modes, the start address should be set at an address location that does not conflict with the display memory of dual panel buffer, which always takes the top memory locations (M) in bytes. M = (Panel Height x Panel Width / 16) x c where c = 1 for monochrome panel = 4 for color panel Table 8-27 : CRT/TV Ink/Cursor Start Address Encoding CRT/TV Ink/Cursor Start Address Bits [7:0] 0 n = 160...1 n = 255...161 Start Address Memory Size - 1024 Memory Size - n x 8192 Invalid Note The effect of this register takes place at the next CRT/TV vertical non-display period. Note See Section 10, "Display Buffer" on page 157 for display buffer organization. CRT/TV Cursor X Position Register 0 REG[082h] CRT/TV Cursor X Position Bit 7 CRT/TV Cursor X Position Bit 6 CRT/TV Cursor X Position Bit 5 CRT/TV Cursor X Position Bit 4 CRT/TV Cursor X Position Bit 3 CRT/TV Cursor X Position Bit 2 CRT/TV Cursor X Position Bit 1 RW CRT/TV Cursor X Position Bit 0 CRT/TV Cursor X Position Register 1 REG[083h] CRT/TV Cursor X Sign n/a n/a n/a n/a n/a CRT/TV Cursor X Position Bit 9 RW CRT/TV Cursor X Position Bit 8 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 134 Epson Research and Development Vancouver Design Center REG[083h] bit 7 CRT/TV Cursor X Sign When this bit = 1, it defines the CRT/TV Cursor X Position register to be a negative number. The negative number should not exceed 63 decimal. When this bit = 0, it defines the CRT/TV Cursor X Position register to be a positive number. CRT/TV Cursor X Position Bits [9:0] A 10-bit register that defines the horizontal position of the CRT/TV Cursor's top left hand corner in pixel units. This register is only valid when Cursor has been selected in the CRT/TV Ink/Cursor select registers. Note REG[082h] bits 7-0 REG[083h] bits 1-0 The effect of REG[082h] through REG[084h] takes place only after REG[085h]is written to and at the next CRT/TV vertical non-display period.The effect of REG[085h] takes place at the next CRT/TV vertical non-display period. CRT/TV Cursor Y Position Register 0 REG[084h] CRT/TV Cursor Y Position Bit 7 CRT/TV Cursor Y Position Bit 6 CRT/TV Cursor Y Position Bit 5 CRT/TV Cursor Y Position Bit 4 CRT/TV Cursor Y Position Bit 3 CRT/TV Cursor Y Position Bit 2 CRT/TV Cursor Y Position Bit 1 RW CRT/TV Cursor Y Position Bit 0 CRT/TV Cursor Y Position Register 1 REG[085h] CRT/TV Cursor Y Sign n/a n/a n/a n/a n/a CRT/TV Cursor Y Position Bit 9 RW CRT/TV Cursor Y Position Bit 8 REG[084h] bit 7 CRT/TV Cursor YSign When this bit = 1, it defines the CRT/TV Cursor Y Position register to be a negative number. The negative number shall not exceed 63 decimal. When this bit = 0, it defines the CRT/TV Cursor Y Position register to be a positive number. CRT/TV Cursor Y Position Bits [9:0] A 10-bit register that defines the vertical position of the CRT/TV Cursor's top left hand corner in pixel units. This register is only valid when Cursor has been selected in the CRT/TV Ink/Cursor select registers. Note REG[084h] bits 7-0 REG[085h] bits 1-0 The effect of REG[082h] through REG[084h] takes place only after REG[085h]is written to and at the next CRT/TV vertical non-display period.The effect of REG[085h] takes place at the next CRT/TV vertical non-display period. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 135 CRT/TV Ink/Cursor Blue Color 0 Register REG[086h] n/a n/a n/a CRT/TV Ink/Cursor Blue Color 0 Bit 4 CRT/TV Ink/Cursor Blue Color 0 Bit 3 CRT/TV Ink/Cursor Blue Color 0 Bit 2 CRT/TV Ink/Cursor Blue Color 0 Bit 1 RW CRT/TV Ink/Cursor Blue Color 0 Bit 0 bits 4-0 CRT/TV Ink/Cursor Blue Color 0 Bits[4:0] These bits define the blue CRT/TV Ink/Cursor color 0. CRT/TV Ink/Cursor Green Color 0 Register REG[087h] n/a n/a RW CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5-0 CRT/TV Ink/Cursor Green Color 0 Bits[5:0] These bits define the green CRT/TV Ink/Cursor color 0. CRT/TV Ink/Cursor Red Color 0 Register REG[088h] n/a n/a n/a CRT/TV Ink/Cursor Red Color 0 Bit 4 CRT/TV Ink/Cursor Red Color 0 Bit 3 CRT/TV Ink/Cursor Red Color 0 Bit 2 CRT/TV Ink/Cursor Red Color 0 Bit 1 RW CRT/TV Ink/Cursor Red Color 0 Bit 0 bits 4-0 CRT/TV Ink/Cursor Red Color 0 Bits[4:0] These bits define the red CRT/TV Ink/Cursor color 0. CRT/TV Ink/Cursor Blue Color 1 Register REG[08Ah] n/a n/a n/a CRT/TV Ink/Cursor Blue Color 1 Bit 4 CRT/TV Ink/Cursor Blue Color 1 Bit 3 CRT/TV Ink/Cursor Blue Color 1 Bit 2 CRT/TV Ink/Cursor Blue Color 1 Bit 1 RW CRT/TV Ink/Cursor Blue Color 1 Bit 0 bits 4-0 CRT/TV Ink/Cursor Blue Color 1 Bits[4:0] These bits define the blue CRT/TV Ink/Cursor color 1. CRT/TV Ink/Cursor Green Color 1 Register REG[08Bh] n/a n/a RW CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV CRT/TV Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 5 Bit 4 bits 5-0 CRT/TV Ink/Cursor Green Color 1 Bits[5:0] These bits define the green CRT/TV Ink/Cursor color 1. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 136 Epson Research and Development Vancouver Design Center CRT/TV Ink/Cursor Red Color 1 Register REG[08Ch] n/a n/a n/a CRT/TV Ink/Cursor Red Color 1 Bit 4 CRT/TV Ink/Cursor Red Color 1 Bit 3 CRT/TV Ink/Cursor Red Color 1 Bit 2 CRT/TV Ink/Cursor Red Color 1 Bit 1 RW CRT/TV Ink/Cursor Red Color 1 Bit 0 bits 4-0 CRT/TV Ink/Cursor Red Color 1 Bits[4:0] These bits define the red CRT/TV Ink/Cursor color 1. CRT/TV Ink/Cursor FIFO High Threshold Register REG[08Eh] CRT/TV Ink/Cursor FIFO High Threshold Bit 3 CRT/TV Ink/Cursor FIFO High Threshold Bit 2 CRT/TV Ink/Cursor FIFO High Threshold Bit 1 RW CRT/TV Ink/Cursor FIFO High Threshold Bit 0 n/a n/a n/a n/a bits 3-0 CRT/TV Ink/Cursor FIFO High Threshold Bits [5:0] These bits are used to optimize the display memory request arbitration for the Hardware Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in hardware. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 137 8.4.12 BitBLT Configuration Registers BitBLT Control Register 0 REG[100h] BitBLT Active Status BitBLT FIFO Not Empty Status (RO) BitBLT FIFO Half Full Status (RO) BitBLT FIFO Full Status(RO) n/a n/a RW BitBLT BitBLT Destination Source Linear Linear Select Select bit 7 BitBLT Active Status This register bit has two data paths, one for write, the other for read. Write Data Path When software writes a one to this bit, it initiates the 2D operation. Read Data Path The read back of this register indicates the status of the 2D engine. When a read from this bit = 1, the 2D engine is busy. When a read from this bit = 0, the 2D engine is idle and is ready for the next operation. Table 8-28 : BitBLT Active Status BitBLT Active Status Write 0 0 1 1 Read 0 1 0 1 State Idle Reserved Initiating operation Operation in progress bit 6 BitBLT FIFO Not-Empty Status This is a read-only status bit. When this bit = 0, the BitBLT FIFO is empty. When this bit = 1, the BitBLT FiFO has at least one data. To reduce system memory read latency, software can monitor this bit prior to a BitBLT read burst operation. The following table shows the number of words available in BitBLT FIFO under different status conditions. Table 8-29: BitBLT FIFO Words Available BitBLT FIFO Full Status (REG[100h] Bit 4) 0 0 0 1 BitBLT FIFO Half Full Status (REG[100h] Bit 5) 0 0 1 1 BitBLT FIFO Not Number of Words available in BitBLT Empty Status FIFO (REG[100h] Bit 6) 0 1 1 1 0 1 to 6 7 to 14 15 to 16 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 138 Epson Research and Development Vancouver Design Center bit 5 BitBLT FIFO Half Full Status This is a read-only status bit. When this bit = 1, the BitBLT FIFO is half full or greater than half full. When this bit = 0, the BitBLT FIFO is less than half full. BitBLT FIFO Full Status This is a read-only status bit. When this bit = 1, the BitBLT FIFO is full. When this bit = 0, the BitBLT FIFO is not full. BitBLT Destination Linear Select When this bit = 1, the Destination BitBLT is stored as a contiguous linear block of memory. When this bit = 0, the Destination BitBLT is stored as a rectangular region of memory. The BitBLT Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address offset from the start of one line to the next line. BitBLT Source Linear Select When this bit = 1, the Source BitBLT is stored as a contiguous linear block of memory. When this bit = 0, the Source BitBLT is stored as a rectangular region of memory. The BitBLT Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address offset from the start of one line to the next line. bit 4 bit 1 bit 0 BitBLT Control Register 1 REG[101h] n/a n/a n/a Reserved n/a n/a n/a RW BitBLT Color Format Select bit 4 bit 0 Reserved. This bit must be set to 0. BitBLT Color Format Select This bit selects the color format that the 2D operation is applied to. When this bit = 0, 8 bpp (256 color) format is selected. When this bit = 1, 16 bpp (64K color) format is selected. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 139 BitBLT ROP Code/Color Expansion Register REG[102h] n/a n/a n/a n/a BitBLT ROP Code Bit 3 BitBLT ROP Code Bit 2 BitBLT ROP Code Bit 1 RW BitBLT ROP Code Bit 0 bits 3-0 BitBLT Raster Operation Code/Color Expansion Bits [3:0] ROP Code for Write BitBLT and Move BitBLT. Bits 2-0 also specify the start bit position for Color Expansion. Table 8-30 : BitBLT ROP Code/Color Expansion Function Selection BitBLT ROP Code Bits [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Boolean Function for Write BitBLT and Move BitBLT 0 (Blackness) ~S . ~D or ~(S + D) ~S . D ~S S . ~D ~D S^D ~S + ~D or ~(S . D) S.D ~(S ^ D) D ~S + D S S + ~D S+D 1 (Whiteness) Boolean Function for Pattern Fill 0 (Blackness) ~P . ~D or ~(P + D) ~P . D ~P P . ~D ~D P^D ~P + ~D or ~(P . D) P.D ~(P ^ D) D ~P + D P P + ~D P+D 1 (Whiteness) Start Bit Position for Color Expansion bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Note S = Source, D = Destination, P = Pattern. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 140 Epson Research and Development Vancouver Design Center BitBLT Operation Register REG[103h] n/a n/a n/a n/a BitBLT Operation Bit 3 BitBLT Operation Bit 2 BitBLT Operation Bit 1 RW BitBLT Operation Bit 0 bits 3-0 BitBLT Operation Bits [3:0] Specifies the 2D Operation to be carried out based on the following table. Table 8-31 : BitBLT Operation Selection BitBLT Operation Bits [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Other combinations Read BitBLT. Move BitBLT in positive direction with ROP. Move BitBLT in negative direction with ROP. Transparent Write BitBLT. Transparent Move BitBLT in positive direction. Pattern Fill with ROP. Pattern Fill with transparency. Color Expansion. Color Expansion with transparency. Move BitBLT with Color Expansion. Move BitBLT with Color Expansion and transparency. Solid Fill. Reserved BitBLT Operation Write BitBLT with ROP. Note The BitBLT operations Pattern Fill with ROP and Pattern Fill with transparency require a BitBLT width > 2 for 8 bpp color depths and a BitBLT width > 1 for 16 bpp color depths. The BitBLT width is set in REG[110h], REG[111h]. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 141 BitBLT Source Start Address Register 0 REG[104h] BitBLT Source Start Address Bit 7 BitBLT Source Start Address Bit 6 BitBLT Source Start Address Bit 5 BitBLT Source Start Address Bit 4 BitBLT Source Start Address Bit 3 BitBLT Source Start Address Bit 2 BitBLT Source Start Address Bit 1 RW BitBLT Source Start Address Bit 0 BitBLT Source Start Address Register 1 REG[105h] BitBLT Source Start Address Bit 15 BitBLT Source Start Address Bit 14 BitBLT Source Start Address Bit 13 BitBLT Source Start Address Bit 12 BitBLT Source Start Address Bit 11 BitBLT Source Start Address Bit 10 BitBLT Source Start Address Bit 9 RW BitBLT Source Start Address Bit 8 BitBLT Source Start Address Register 2 REG[106h] n/a n/a n/a BitBLT Source Start Address Bit 20 BitBLT Source Start Address Bit 19 BitBLT Source Start Address Bit 18 BitBLT Source Start Address Bit 17 RW BitBLT Source Start Address Bit 16 REG[104h] bits 7-0 REG[105h] bits 7-0 REG[106h] bits 4-0 BitBLT Source Start Address Bits [20:0] A 21-bit register that specifies the source start address for the BitBLT operation. If data is sourced from the CPU, then bit 0 is used for byte alignment within a 16-bit word and the other address bits are ignored. In pattern fill operation, the BitBLT Source Start Address is defined by the following equation. Value programmed to the Source Start Address Register = Pattern Base Address + Pattern Line Offset + Pixel Offset. The following table shows how Source Start Address Register is defined for 8 and 16 bpp color depths. Table 8-32 : BitBLT Source Start Address Selection Color Format 8 bpp 16 bpp Pattern Base Address[20:0] BitBLT Source Start Address[20:6] BitBLT Source Start Address[20:7] Pattern Line Offset[2:0] BitBLT Source Start Address[5:3] BitBLT Source Start Address[6:4] Pixel Offset[3:0] BitBLT Source Start Address[2:0] BitBLT Source Start Address[3:0] Note For further information on the BitBLT Source Start Address register, see the S1D13806 Programming Notes and Examples, document number X28B-G-003-xx. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 142 Epson Research and Development Vancouver Design Center BitBLT Destination Start Address Register 0 REG[108h] RW BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Destination Destination Destination Destination Destination Destination Destination Destination Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BitBLT Destination Start Address Register 1 REG[109h] RW BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Destination Destination Destination Destination Destination Destination Destination Destination Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 BitBLT Destination Start Address Register 2 REG[10Ah] n/a n/a n/a RW BitBLT BitBLT BitBLT BitBLT BitBLT Destination Destination Destination Destination Destination Start Address Start Address Start Address Start Address Start Address Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 REG[108h] bits 7-0 REG[109h] bits 7-0 REG[10Ah] bits 4-0 BitBLT Destination Start Address Bits [20:0] A 21-bit register that specifies the destination start address for the BitBLT operation. BitBLT Memory Address Offset Register 0 REG[10Ch] BitBLT Memory Address Offset Bit 7 BitBLT Memory Address Offset Bit 6 BitBLT Memory Address Offset Bit 5 BitBLT Memory Address Offset Bit 4 BitBLT Memory Address Offset Bit 3 BitBLT Memory Address Offset Bit 2 BitBLT Memory Address Offset Bit 1 RW BitBLT Memory Address Offset Bit 0 BitBLT Memory Address Offset Register 1 REG[10Dh] n/a n/a n/a n/a n/a BitBLT Memory Address Offset Bit 10 BitBLT Memory Address Offset Bit 9 RW BitBLT Memory Address Offset Bit 8 REG[10Ch] bits 7-0 REG[10Dh] bits 2-0 BitBLT Memory Address Offset Bits [10:0] These bits are the display's 11-bit address offset from the starting word of line n to the starting word of line n + 1. They are used only for address calculation when the BitBLT is configured as a rectangular region of memory. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 143 BitBLT Width Register 0 REG[110h] BitBLT Width Bit 7 BitBLT Width Bit 6 BitBLT Width Bit 5 BitBLT Width Bit 4 BitBLT Width Bit 3 BitBLT Width Bit 2 BitBLT Width Bit 1 RW BitBLT Width Bit 0 BitBLT Width Register 1 REG[111h] n/a n/a n/a n/a n/a n/a BitBLT Width Bit 9 RW BitBLT Width Bit 8 REG[110h] bits 7-0 REG[111h] bits 1-0 BitBLT Width Bits [9:0] A 10-bit register that specifies the BitBLT width in pixels - 1. BitBLT width in pixels = (ContentsOfThisRegister) + 1 Note The BitBLT operations Pattern Fill with ROP and Pattern Fill with transparency require a BitBLT width > 2 for 8 bpp color depths and a BitBLT width > 1 for 16 bpp color depths. BitBLT Height Register 0 REG[112h] RW BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BitBLT Height Register 1 REG[113h] n/a n/a n/a n/a n/a n/a RW BitBLT Height BitBLT Height Bit 9 Bit 8 REG[112h] bits 7-0 REG[113h] bits 1-0 BitBLT Height Bits [9:0] A 10-bit register that specifies the BitBLT height in lines - 1. BitBLT height in lines = (ContentsOfThisRegister) + 1 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 144 Epson Research and Development Vancouver Design Center BitBLT Background Color Register 0 REG[114h] BitBLT Background Color Bit 7 BitBLT Background Color Bit 6 BitBLT Background Color Bit 5 BitBLT Background Color Bit 4 BitBLT Background Color Bit 3 BitBLT Background Color Bit 2 BitBLT Background Color Bit 1 RW BitBLT Background Color Bit 0 BitBLT Background Color Register 1 REG[115h] BitBLT Background Color Bit 15 BitBLT Background Color Bit 14 BitBLT Background Color Bit 13 BitBLT Background Color Bit 12 BitBLT Background Color Bit 11 BitBLT Background Color Bit 10 BitBLT Background Color Bit 9 RW BitBLT Background Color Bit 8 REG[114h] bits 7-0 REG[115h] bits 15-8 BitBLT Background Color Bits [15:0] A 16-bit register that specifies the BitBLT background color for Color Expansion or key color for Transparent BitBLT. For 16 bpp color depths (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depths (REG[101h] bit 0 = 0), only bits 7-0 are used. BitBLT Foreground Color Register 0 REG[118h] BitBLT Foreground Color Bit 7 BitBLT Foreground Color Bit 6 BitBLT Foreground Color Bit 5 BitBLT Foreground Color Bit 4 BitBLT Foreground Color Bit 3 BitBLT Foreground Color Bit 2 BitBLT Foreground Color Bit 1 RW BitBLT Foreground Color Bit 0 BitBLT Foreground Color Register 1 REG[119h] BitBLT Foreground Color Bit 15 BitBLT Foreground Color Bit 14 BitBLT Foreground Color Bit 13 BitBLT Foreground Color Bit 12 BitBLT Foreground Color Bit 11 BitBLT Foreground Color Bit 10 BitBLT Foreground Color Bit 9 RW BitBLT Foreground Color Bit 8 REG[118h] bits 7-0 REG[119h] bits 7-0 BitBLT Foreground Color Bits [15:0] A 16-bit register that specifies the BitBLT foreground color for Color Expansion or Solid Fill. For 16 bpp color depths (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depths (REG[101h] bit 0 = 0), only bits 7-0 are used. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 145 8.4.13 Look-Up Table Registers Note Accessing the LCD Look-Up Table (LUT) requires an active LCD PCLK and accessing the CRT/TV LUT requires an active CRT/TV PCLK. For further information on the clocks, see Section 7, "Clocks" on page 92. Look-Up Table Mode Register REG[1E0h] n/a n/a n/a n/a n/a n/a LUT Mode Bit 1 RW LUT Mode Bit 0 bits 1-0 Look-Up Table Mode Bits [1:0] These bits determine which of the on-chip Look-Up Tables (LUT) (LCD and CRT/TV) are accessible by REG[1E2h] and REG[1E4h]. Table 8-33 : LUT Mode Selection LUT Mode Bits [1:0] 00 01 10 11 Read LCD LUT LCD LUT CRT/TV LUT Reserved Write LCD and CRT/TV LUT's LCD LUT CRT/TV LUT Reserved Look-Up Table Address Register REG[1E2h] LUT Address Bit 7 LUT Address Bit 6 LUT Address Bit 5 LUT Address Bit 4 LUT Address Bit 3 LUT Address Bit 2 LUT Address Bit 1 RW LUT Address Bit 0 bits 7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13806 has three 256-position, 4-bit wide LUTs, one for each of red, green, and blue - refer to Section 12, "Look-Up Table Architecture" on page 161 for details. This register selects which LUT entry is read/write accessible through the LUT Data Register (REG[1E4h]). Writing the LUT Address Register automatically sets the pointer to the Red LUT. Accesses to the LUT Data Register automatically increment the pointer. For example, writing a value 03h into the LUT Address Register sets the pointer to R[3]. A subsequent access to the LUT Data Register accesses R[3] and moves the pointer onto G[3]. Subsequent accesses to the LUT Data Register move the pointer onto B[3], R[4], G[4], B[4], R[5], etc. Note The RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be written before the LUT is updated. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 146 Epson Research and Development Vancouver Design Center Look-Up Table Data Register REG[1E4h] LUT Data Bit 3 LUT Data Bit 2 LUT Data Bit 1 LUT Data Bit 0 n/a n/a n/a RW n/a bits 7-4 LUT Data Bits [3:0] This register is used to read/write the RGB Look-Up Tables. This register accesses the entry at the pointer controlled by the Look-Up Table Address register (REG[1E2h]). Accesses to the Look-Up Table Data register automatically increment the pointer. Note The RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be written before the LUT is updated. 8.4.14 Power Save Configuration Registers For further information on Power Save Mode, refer to Section 19, "Power Save Mode" on page 202. Power Save Configuration Register REG[1F0h] n/a n/a n/a Reserved n/a n/a n/a RW Power Save Mode Enable bit 4 bit 0 Reserved. This bit must be set to 1. Power Save Mode Enable When this bit = 1, power save mode is enabled. When this bit = 0, power save mode is disabled. Note For details on Power Save Mode, see Section 19, "Power Save Mode" on page 202. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 147 Power Save Status Register REG[1F1h] n/a n/a n/a n/a n/a n/a LCD Power Save Status RO Memory Controller Power Save Status bit 1 LCD Power Save Status This bit indicates the power save state of the LCD panel. When this bit = 1, the panel is powered down. When this bit = 0, the panel is powered up, or in transition of powering up or down. Note When this bit reads a 1, the system may safely shut down the LCD pixel clock source. Note When the LCD panel is not enabled (REG[1FCh] bit 0 = 0), this bit returns a 1. bit 0 Memory Controller Power Save Status This bit indicates the power save state of the memory controller. When this bit = 1, the memory controller is powered down and the SDRAM is in self refresh mode. When this bit = 0, the memory controller is powered up and is in normal mode. Note When this bit reads a 1, the system may safely shut down the memory clock source. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 148 Epson Research and Development Vancouver Design Center 8.4.15 Miscellaneous Registers CPU-to-Memory Access Watchdog Timer Register REG[1F4h] n/a n/a Mem. Access Watchdog Timer bit 5 Mem. Access Watchdog Timer bit 4 Mem. Access Watchdog Timer bit 3 Mem. Access Watchdog Timer bit 2 Mem. Access Watchdog Timer bit 1 RW Mem. Access Watchdog Timer bit 0 bits 5-0 CPU-to-Memory Access Watchdog Timer Bits [5:0] A non-zero value in this register enables the watchdog timer for CPU-to-memory access. When enabled, any CPU-to-memory access cycle is completed successfully within a time determined by the following equation. Maximum CPU-to-memory access cycle time = (8n + 7) x Tbclk + 13 x Tmclk where: n = A non-zero value in this register Tbclk = Bus clock period, or Bus clock period x 2 (if CONF5 = 1, see Table 4-9 on page 33) Tmclk = Memory clock period This function is required by some busses which time-out if the cycle duration exceeds a certain time period. This function is not intended to arbitrarily shorten the CPU-to-memory access cycle time in order gain higher CPU bandwidth. Doing so may significantly reduce the available display refresh bandwidth which may cause display corruption. This register does not affect CPU-to-register access or BitBLT access. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 149 8.4.16 Common Display Mode Register Display Mode Register REG[1FCh] n/a SwivelView Enable Bit 0 n/a n/a n/a Display Mode Select Bit 2 Display Mode Select Bit 1 RW Display Mode Select Bit 0 bit 6 SwivelView Enable Bit 0 When this bit = 1, the LCD and CRT display image is rotated 90 clockwise. When this bit = 0, there is no hardware effect. This bit in conjunction with SwivelViewTM Enable Bit 1 achieves the following hardware rotations. Table 8-34: Setting SwivelView Modes SwivelView Enable Bits SwivelView Enable Bit 0 (REG[1FCh] bit 6) SwivelView Enable Bit 1 (REG[040h] bit 4) SwivelViewTM Modes Normal 0 0 SwivelView 90 1 0 SwivelView 180 0 1 SwivelView 270 1 1 Note Please refer to Section 15, "SwivelViewTM" on page 177 for application and limitations. bits 2-0 Display Mode Select Bits [2:0] These bits select the display model according to the following table. The LCD display mode is enabled/disabled using bit 0. Table 8-35: Display Mode Selection Display Mode Select Bits [2:0] 000 001 010 011 100 101 110 111 Display Mode Enabled no display LCD only CRT only EISD (CRT and LCD) TV with flicker filter off EISD (TV with flicker filter off and LCD) TV with flicker filter on EISD (TV with flicker filter on and LCD) Note REG[018h] bit 7 must be set to 1 when the flicker filter is enabled. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 150 Epson Research and Development Vancouver Design Center Note The Flicker Filter reduces the "flickering" effect seen on interlaced displays by averaging adjacent lines on the TV display. This "flickering" is caused by sharp vertical image transitions that occur over one line (1 vertical pixel). For example, one pixel high lines, edges of window boxes, etc. Flickering occurs because these high resolution lines are effectively displayed at half the refresh frequency due to interlacing. 8.5 MediaPlug Registers Descriptions The S1D13806 has built-in support for Winnov's MediaPlug connection designed for video cameras. The following registers are used to control the connection and accept data from the camera. The MediaPlug registers decode A11-A0 and require A20 = 0 and A12 = 1. The MediaPlug registers are 16-bit wide. Byte access to the MediaPlug registers is not allowed. For further information, see Section 17, "MediaPlug Interface" on page 188. Note The MediaPlug control registers must not be accessed while Power Save Mode is enabled (REG[1F0h] bit 0 = 1). 8.5.1 MediaPlug Control Registers MediaPlug LCMD Register REG[1000h] LCMD Bit 7 LCMD Bit 15 LCMD Bit 6 LCMD Bit 14 LCMD Bit 5 LCMD Bit 13 LCMD Bit 4 LCMD Bit 12 LCMD Bit 3 LCMD Bit 11 LCMD Bit 2 LCMD Bit 10 LCMD Bit 1 LCMD Bit 9 RW LCMD Bit 0 LCMD Bit 8 REG[1000h] bits 15-0 MediaPlug LCMD Bits [15:0] A 16-bit register for setting and detecting various modes of operation of the MediaPlug Local Slave. This register is handled differently for reads and writes. The following table shows the MediaPlug description of the LCMD Register. See bit descriptions for details. Table 8-36: MediaPlug LCMD Read/Write Descriptions Data Write Read Data Write Read D7 D15 D14 D13 00b D6 Xxxx Rstat[2:0] 0b D5 D4 D3 IC IC D12 D11 D10 D9 D8 TO[2:0] TO[2:0] Xxxxxx Rev[3:0] D2 MC MC D1 P P D0 W W bits 15-14 Timeout Option These bits select the timeout delay in MediaPlug clock cycles. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 151 Table 8-37: Timeout Option Delay Timeout Option Bits[15:14] 00 01 10 11 Timeout (MediaPlug clock cycles) 1023 (default) 64 128 64 bits 13-12 bits 11-8 A read from these bits always returns 00b. A write to these bits has no hardware effect. MediaPlug IC Revision The revision for this MediaPlug IC is "0011b". A write to these bits has no hardware effect. Cable Detected Status The cable detected status as determined by the MPD(1) pin. When this bit = 0, a MediaPlug cable is connected. When this bit = 1, a MediaPlug cable is not detected. A write to this bit has no hardware effect. A read from this bit always returns 0b. A write to this bit has no hardware effect. Remote Powered Status The remote powered status as determined by the RCTRL pin. When this bit = 0, the remote is not powered. When this bit = 1, the remote is powered and connected. A write to this bit has no hardware effect. Table 8-38: Cable Detect and Remote Powered Status Cable Detected Remote Powered Status [bit 7] Status [bit 5] 0 0 1 0 1 x Status cable connected but remote not powered cable connected and remote powered cable not connected bit 7 bit 6 bit 5 bit 4 bit 3 A read from this bit always returns 0b. A write to this bit has no hardware effect. MediaPlug Clock Enable When this bit = 0, the MediaPlug clock is disabled (default). When this bit = 1, the MediaPlug clock is enabled. MediaPlug Clock When this bit = 0, the MediaPlug cable clock (VMPCLK) is disabled (default). When this bit = 1, the MediaPlug cable clock (VMPCLK) is enabled. bit 2 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 152 Epson Research and Development Vancouver Design Center bit 1 Power Enable to Remote When this bit = 0, power to remote is off (default). When this bit =1, power to remote is on. Watchdog Disable When this bit = 0, the MediaPlug watchdog is enabled (default). When this bit = 1, the MediaPlug watchdog is disabled. bit 0 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 153 MediaPlug Reserved LCMD Register REG[1002h] LCMD Bit 23 LCMD Bit 31 LCMD Bit 22 LCMD Bit 30 LCMD Bit 21 LCMD Bit 29 LCMD Bit 20 LCMD Bit 28 LCMD Bit 19 LCMD Bit 27 LCMD Bit 18 LCMD Bit 26 LCMD Bit 17 LCMD Bit 25 RW LCMD Bit 16 LCMD Bit 24 REG[1002h] bits 15-0 MediaPlug Reserved LCMD Bits [15:0] This register is not implemented and is reserved for future expansion of the LCMD register. A write to this register has no hardware effect. A read from this register always return 0000h. MediaPlug CMD Register REG[1004h] CMD Bit 7 CMD Bit 15 CMD Bit 6 CMD Bit 14 CMD Bit 5 CMD Bit 13 CMD Bit 4 CMD Bit 12 CMD Bit 3 CMD Bit 11 CMD Bit 2 CMD Bit 10 CMD Bit 1 CMD Bit 9 RW CMD Bit 0 CMD Bit 8 REG[1002h] bits 15-0 MediaPlug CMD Bits [15:0] A 16-bit register for setting the MediaPlug commands. This register is handled differently for reads and writes. The following table shows the MediaPlug description of the CMD Register. See bit descriptions for details. Table 8-39: MediaPlug CMD Read/Write Descriptions Data Write Read Data Write Read D D7 T D6 D5 I[4:0] I[4:0] D4 D3 D15 D14 D13 D12 I[12:5] I[10:5] D2 D1 C[2:0] C[2:0] D0 D11 D10 D9 D8 bit 15 Dirty Bit This bit is set by the hardware when the command register is written. It is cleared by hardware by the following conditions: 1. Remote-Reset (After this command has been acknowledged by remote. 2. End_Stream (After this command has been acknowledged by remote. 3. Write to DATA register if the CCC field is Write_Reg. 4. Read to DATA register if the CCC field is Read_Reg. It is also set when the Remote Machine loses power or the cable is disconnected. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 154 Epson Research and Development Vancouver Design Center bit 14 Timeout Bit It is set when Watchdog is enabled and MediaPlug read or write cycle takes longer than 64, 128, 1024 cycles of MediaPlug clock depending on LCMD register settings. It is also set when the remote is not powered. It is cleared at the beginning of every command write by the host. Index Field This field is the address presented by the remote to the remote function. MediaPlug transmits the entire 16-bits of the first word of the command Register as written, but I12 (D15) and I11 (D14) are hidden from readback by the dirty bit and Watchdog error bit. Command Field Selects the command as follows: Table 8-40: MediaPlug Commands Command Field [bits 2:0] 000 001 010 011 100 101 110 111 Command Remote-Reset: Hardware reset of remote. Stream-End: Indicates end of data streaming operation. Write-Register: Write remote register INDEX[5:0] with DATA. Read-Register: Read remote register INDEX[5:0] to DATA. Write_Stream: Begin streaming data to the remote. NOP: The command is sent across the MediaPlug. There is no other effect. NOP: The command is sent across the MediaPlug. There is no other effect. Read-Stream: Begin streaming data from the remote. bits 13-3 bit 2-0 MediaPlug Reserved CMD Register REG[1006h] CMD Bit 23 CMD Bit 31 CMD Bit 22 CMD Bit 30 CMD Bit 21 CMD Bit 29 CMD Bit 20 CMD Bit 28 CMD Bit 19 CMD Bit 27 CMD Bit 18 CMD Bit 26 CMD Bit 17 CMD Bit 25 RW CMD Bit 16 CMD Bit 24 REG[1006h] bits 15-0 MediaPlug Reserved CMD Bits [15:0] This register is not implemented and is reserved for future expansion of the CMD register. A write to this register has no hardware effect. A read from this register always return 0000h. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 155 8.5.2 MediaPlug Data Registers MediaPlug Data Register REG[1008h] to REG[1FFEh], even address Data Bit 7 Data Bit 15 Data Bit 6 Data Bit 14 Data Bit 5 Data Bit 13 Data Bit 4 Data Bit 12 Data Bit 3 Data Bit 11 Data Bit 2 Data Bit 10 Data Bit 1 Data Bit 9 RW Data Bit 0 Data Bit 8 Data Register bits 15-0 MediaPlug Data Bits [15:0] A 16-bit register used for read/write and streaming read/write of MediaPlug data. This register is loosely decoded from 1008h to 1FFEh so that the port may be accessed using DWORD block transfer instructions. 8.6 BitBLT Data Registers Descriptions The BitBLT data registers decode A19-A0 and require A20 = 1. The BitBLT data registers are 16-bit wide. Byte access to the BitBLT data registers is not allowed. BitBLT Data Register 0 A20-A0 = 100000h-1FFFFEh, even address Data Bit 7 Data Bit 15 Data Bit 6 Data Bit 14 Data Bit 5 Data Bit 13 Data Bit 4 Data Bit 12 Data Bit 3 Data Bit 11 Data Bit 2 Data Bit 10 Data Bit 1 Data Bit 9 RW Data Bit 0 Data Bit 8 Data Register bits 15-0 BitBLT Data Bits [15:0] A 16-bit register that specifies the BitBLT data. This register is loosely decoded from 100000h to 1FFFFEh. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 156 Epson Research and Development Vancouver Design Center 9 2D BitBLT Engine 9.1 Overview The S1D13806 is designed with a built-in 2D BitBLT engine which increases the performance of Bit Block Transfers (BitBLT). It supports 8 and 16 bit-per-pixel color depths. The BitBLT engine supports rectangular and linear addressing modes for source and destination in a positive direction for all BitBLT operations except the move BitBLT which also supports in a negative direction. The BitBLT operations support byte alignment of all types. The BitBLT engine has a dedicated BitBLT IO access space allowing it to support multi-tasking applications. This allows the BitBLT engine to support simultaneous BitBLT and CPU read/write operations. 9.2 BitBLT Operations The S1D13806 2D BitBLT engine supports the following BitBLTs. For detailed information on using the individual BitBLT operations, refer to the S1D13806 Programming Notes and Examples, document number X28B-G-003-xx. * Write BitBLT. * Move BitBLT. * Solid Fill BitBLT. * Pattern Fill BitBLT. * Transparent Write BitBLT. * Transparent Move BitBLT. * Read BitBLT. * Color Expansion BitBLT. * Move BitBLT with Color Expansion. Note For details on the BitBLT registers, see Section 8.4.12, "BitBLT Configuration Registers" on page 137. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 157 10 Display Buffer The system addresses the display buffer using CS#, M/R#, and the input pins AB[20:0]. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table below: Table 10-1 : S1D13806 Addressing CS# M/R# Access Register access - see Section 8.2, "Register Mapping" on page 97. 0 0 * REG[000h] is addressed when AB[12:0] = 0 * REG[001h] is addressed when AB[12:0] = 1 * REG[n] is addressed when AB[12:0] = n Memory access: the 1.25M byte display buffer is addressed by AB[20:0] S1D13806 not selected 0 1 1 X The display buffer address space is always 2M bytes. However, the physical display buffer is 1280k bytes. The space above the 1280k boundary is unavailable (see Figure 10-1: "Display Buffer Addressing"). The display buffer can contain an image buffer, one or more Ink Layer/Hardware Cursor buffers, and a dual panel buffer. AB[20:0] 00 0000h 1280k Byte Buffer Image Buffer Ink/Cursor Buffer 13 FFFFh 14 0000h Dual Panel Buffer Unavailable 1F FFFFh Figure 10-1: Display Buffer Addressing Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 158 Epson Research and Development Vancouver Design Center 10.1 Image Buffer The image buffer contains the formatted display mode data - see Section 11.1, "Display Mode Data Format" on page 159. The displayed image(s) may occupy only a portion of this space with the remaining area used for multiple images - possibly for animation or general storage. Section 11, "Display Configuration" on page 159 for the relationship between the image buffer and the displayed image. 10.2 Ink Layer/Hardware Cursor Buffers The Ink Layer/Hardware Cursor buffers contain formatted image data for the Ink Layer and Hardware Cursor. There may be several Ink Layer/Hardware Cursor images stored in the display buffer but only one may be active at any given time. For further information, see Section 14, "Ink Layer/Hardware Cursor Architecture" on page 173. 10.3 Dual Panel Buffer In dual panel mode with the dual panel buffer enabled, the top of the display buffer is allocated to the dual panel buffer. The size of the dual panel buffer is a function of the panel resolution and the type of panel (color or monochrome). Dual Panel Buffer Size (in bytes) = (panel width x panel height) x factor / 16 where factor: = 4 for color panel = 1 for monochrome panel Note Calculating the size of the dual panel buffer is required to avoid overwriting the Hardware Cursor/Ink Layer buffer. Example 1: For a 800x600 color panel the dual panel buffer size is 120,000 bytes. With a 1280k byte display buffer, the dual panel buffer resides from 12 2b40h to 13 FFFFh. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 159 11 Display Configuration 11.1 Display Mode Data Format The following diagram show the display mode data formats for a little endian system. . 4 bpp: Byte 0 Byte 1 Byte 2 Host Address 8 bpp: bit 7 A0 A2 A4 B0 B2 B4 C0 C2 C4 D0 D2 D4 A1 A3 A5 B1 B3 B5 C1 C3 C5 bit 0 D1 D3 D5 LUT P0 P1 P2 P3 P4 P5 P6 P7 Pn = RGB value from LUT Index (An, Bn, Cn, Dn) Panel Display Display Buffer bit 7 Byte 0 Byte 1 Byte 2 Host Address A0 A1 A2 B0 B1 B2 C0 C1 C2 D0 D1 D2 E0 E1 E2 F0 F1 F2 G0 G1 G2 bit 0 H0 H1 H2 LUT P0 P1 P2 P3 P4 P5 P6 P7 Pn = RGB value from LUT Index (An, Bn, Cn, Dn,En, Fn, Gn, Hn) Panel Display Display Buffer 16 bpp: bit 7 Byte 0 Byte 1 Byte 2 Byte 3 Host Address G02 G01 5-6-5 RGB bit 0 P0 P1 P2 P3 P4 P5 P6 P7 G00 B04 B03 B02 B01 B00 Bypasses LUT Pn = (R n4-0, Gn 5-0, Bn4-0) R04 R03 R02 R01 R00 G05 G04 G03 G12 R1 4 G11 R1 3 G1 R1 0 B1 4 1 B13 R1 0 B12 G15 B11 G14 B1 0 2 R1 G13 Panel Display Display Buffer Figure 11-1: 4/8/16 Bit-per-pixel Format Memory Organization Note 1. The Host-to-Display mapping shown here is for a little endian system. 2. For the 16 bit-per-pixel format, Rn, Gn, Bn represent the red, green, and blue color components. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 160 Epson Research and Development Vancouver Design Center 11.2 Image Manipulation The figure below shows how the screen image is stored in the image buffer and positioned on the LCD display. The screen image on the CRT/TV is manipulated similarly. When EISD is enabled (see Section 16, "EPSON Independent Simultaneous Display (EISD)" on page 186), the images on the LCD and on the CRT/TV are independent of each other. * For LCD: (REG[047h], REG[046h]) define the width of the virtual image. For CRT/TV: (REG[067h], REG[066h]) define the width of the virtual image. * For LCD: (REG[044h], REG[043h], REG[042h]) define the starting word of the displayed image. For CRT/TV: (REG[064h], REG[063h], REG[062h]) define the starting word of the displayed image. * For LCD: REG[048h] defines the starting pixel within the starting word. For CRT/TV: REG[068h] defines the starting pixel within the starting word. * For LCD: REG[032h] defines the width of the LCD display. For CRT/TV: REG[050h] defines the width of the CRT/TV display. * For LCD: (REG[039h], REG[038h]) define the height of the LCD display. For CRT/TV: (REG[057h], REG[056h]) define the height of the CRT/TV display. Image Buffer Starting Word (REG[044h], REG[043h], REG[042h]) Starting Pixel of Word (REG[048h]) LCD Display Height of LCD Display ((REG[039h], REG[038h]) + 1) lines Screen Line 0 Line 1 Screen Width of LCD Display ((REG[032h] + 1) x 8) pixels Width of Virtual Image (REG[047h], REG[046h]) Figure 11-2: Image Manipulation S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 161 12 Look-Up Table Architecture The following depictions are intended to show the display data output path only. 12.1 Monochrome Modes The green LUT is used for all monochrome modes. 4 Bit-Per-Pixel Monochrome Mode 4 bit-per-pixel data from Image Buffer Green Look-Up Table 256x4 00 01 1 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FC FD FE FF 0 1 0 4-bit Grey Data: 1010 (0Ah) FRM BLOCK Output to display example data: 0001 (01h) = unused Look-Up Table entries Figure 12-1: 4 Bit-Per-Pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 162 Epson Research and Development Vancouver Design Center 8 Bit-Per-Pixel Monochrome Mode 8 bit-per-pixel data from Image Buffer Green Look-Up Table 256x4 00 01 1 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FC FD FE FF 0 1 0 4-bit Grey Data: 1010 (0Ah) FRM BLOCK Output to display example data: 0000 0001 (01h) Figure 12-2: 8 Bit-Per-Pixel Monochrome Mode Data Output Path 16 Bit-Per-Pixel Monochrome Mode A color depth of 16 bpp is required to achieve 64 gray shades in monochrome mode. In this mode the LUT is bypassed and the green component of the pixel is mapped to the FRM. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 163 12.2 Color Modes 4 Bit-Per-Pixel Color Mode 4 bit-per-pixel data from Image Buffer example data: 0001 (01h) Red Look-Up Table 256x4 00 01 1 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FC FD FE FF Green Look-Up Table 256x4 00 01 0 1 0 1 02 4-bit Green Data: 03 0101 (05h) 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FC FD FE FF Blue Look-Up Table 256x4 00 01 1 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FC FD FE FF = unused Look-Up Table entries 1 1 1 4-bit Blue Data: 1111 (0Fh) 0 1 0 4-bit Red Data: 1010 (0Ah) FRM BLOCK Output to display example data: 0001 (01h) example data: 0001 (01h) Figure 12-3: 4 Bit-Per-Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 164 Epson Research and Development Vancouver Design Center 8 Bit-Per-Pixel Color Mode Red Look-Up Table 256x4 00 01 1 0 1 0 02 4-bit Red Data: example data: 00000001 (01h) 03 1010 (0Ah) 04 05 06 07 F8 F9 FA FB FC FD FE FF Green Look-Up Table 256x4 00 01 0 1 0 1 02 4-bit Green Data: example data: 00000001 (01h) 03 0101 (05h) 04 05 06 07 F8 F9 FA FB FC FD FE FF 8 bit-per-pixel data from Image Buffer FRM BLOCK Output to display Blue Look-Up Table 256x4 00 01 1 1 1 1 02 4-bit Blue Data: example data: 00000001 (01h) 03 1111 (0Fh) 04 05 06 07 F8 F9 FA FB FC FD FE FF = unused Look-Up Table entries Figure 12-4: 8 Bit-Per-Pixel Color Mode Data Output Path 16 Bit-Per-Pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode - Section 11, "Display Configuration" on page 159. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 165 13 TV Considerations 13.1 NTSC/PAL Operation NTSC or PAL video is supported in either composite or S-video format. Filters may be enabled to reduce the distortion associated with displaying high resolution computer images on an interlaced TV display. The image can be vertically and horizontally positioned on the TV. Additionally, a dedicated Hardware Cursor (independent from the LCD display) is supported. 13.2 Clock Source The required clock frequencies for NTSC/PAL are given in the following table. Table 13-1 : Required Clock Frequencies for NTSC/PAL TV Format NTSC PAL Required Clock Frequency 14.318180 MHz (3.579545 MHz subcarrier) 17.734475 MHz (4.43361875 MHz subcarrier) Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 166 Epson Research and Development Vancouver Design Center 13.3 Filters When displaying computer images on a TV, several image distortions are likely to arise: * cross-luminance distortion. * cross-chrominance distortion. * flickering. These distortions are caused by the high-resolution nature of computer images which typically contain sharp color transitions, and sharp luminance transitions (e.g., high contrast one pixel wide lines and fonts, window edges, etc.). Three filters are available to reduce these distortions. 13.3.1 Chrominance Filter (REG[05Bh] bit 5) The chrominance filter adjusts the color of the TV by limiting the bandwidth of the chrominance signal (reducing cross-luminance distortion). This reduces the "ragged edges" seen at boundaries between sharp color transitions. This filter is controlled using REG[05Bh] bit 5 and is most useful for composite video output. 13.3.2 Luminance Filter (REG[05Bh] bit 4) The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the luminance signal (reducing cross-chrominance distortion). This reduces the "rainbow-like" colors at boundaries between sharp luminance transitions. This filter is controlled using REG[05Bh] bit 4 and is most useful for composite video output. 13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1]) The "flickering" effect seen on interlaced displays is caused by sharp vertical image transitions that occur over one line (1 vertical pixel). For example, one pixel high lines, edges of window boxes, etc. Flickering occurs because these high resolution lines are effectively displayed at half the refresh frequency due to interlacing. The anti-flicker filter averages adjacent lines on the TV display to reduce flickering. This filter is controlled using the Display Mode register (REG[1FCh] bits [2:1]). Note When TV with anti-flicker filter is enabled, the Flicker Filter Clock Enable bit (REG[18h] bit 7) must be set to 1. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 167 13.4 TV Output Levels Vwhite Vyellow Vcyan Vgreen Vmagenta Vred Vblue Vblank Vblack Vsync Figure 13-1: NTSC/PAL SVideo-Y (Luminance) Output Levels Table 13-2 : NTSC/PAL SVideo-Y (Luminance) Output Levels Symbol Vwhite Vyellow Vcyan Vgreen Vmagenta Vred Vblue Vblack Vblanking Vsync White Yellow Cyan Green Magenta Red Blue Black Blanking Sync Tip Parameter RGB 1F 3F 1F 1F 3F 00 00 3F 1F 00 3F 00 1F 00 1F 1F 00 00 00 00 1F 00 00 00 N.A. N.A. NTSC / PAL (mv) 996 923 798 725 608 536 410 338 284 0 NTSC / PAL (IRE) 99.5 89 72 62 45 35 17 7.3 0 -40 Note RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 168 Epson Research and Development Vancouver Design Center V1cyan V1green V1magenta V1red V1yellow V1blue V1burst Vblanking V2burst V2yellow V2blue V2green V2cyan V2magenta V2red Figure 13-2: NTSC/PAL SVideo-C (Chrominance) Output Levels Table 13-3 : NTSC/PAL SVideo-C (Chrominance) Output Levels Symbol V1burst V1yellow V1cyan V1green V1magenta V1red V1blue Vblanking V2burst V2yellow V2cyan V2green V2magenta V2red V2blue Parameter Burst positive peak Yellow positive peak Cyan positive peak Green positive peak Magenta positive peak Red positive peak Blue positive peak Blanking Burst negative peak Yellow negative peak Cyan negative peak Green negative peak Magenta negative peak Red negative peak Blue negative peak RGB N.A. 3F 00 3F 1F 3F 00 00 1F 00 00 00 1F N.A. N.A. 1F 3F 00 00 3F 1F 00 3F 00 1F 00 1F 1F 00 00 00 00 1F 1F 00 00 1F 1F 00 NTSC / PAL (mv) 552 / 541 700 815 751 751 815 700 410 268 / 279 121 5 70 70 5 121 NTSC / PAL (IRE) 20 / 18.5 40.8 57 48 48 57 40.8 0 -20 / -18.5 -40.8 -57 -48 -48 -57 -40.8 Note RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 169 V1 yellow V1cyan V1green Vwhite V2yellow V2cyan V2green V3yellow V2magenta V2red V1burst Vblank Vblack V3cyan V3green V2burst V3magenta V3red V3blue V2blue V1magenta V1red V1blue Vsync Figure 13-3: NTSC/PAL Composite Output Levels Table 13-4 : NTSC/PAL Composite Output Levels Symbol V1yellow V1cyan V1green V1magenta V1red V1blue Vwhite V2yellow V2cyan V2green V2magenta V2red V2blue Vblack V3yellow V3cyan V3green V3magenta V3red V3blue Vblank V1burst V2burst Vsync Parameter Yellow chrominance positive peak Cyan chrominance positive peak Green chrominance positive peak Magenta chrominance positive peak Red chrominance positive peak Blue chrominance positive peak White luminance level Yellow luminance level Cyan luminance level Green luminance level Magenta luminance level Red luminance level Blue luminance level Black luminance level Yellow chrominance negative peak Cyan chrominance negative peak Green chrominance negative peak Magenta chrominance negative peak Red chrominance negative peak Blue chrominance negative peak Blank Level Burst positive peak Burst negative peak Sync Tip RGB 1F 3F 00 00 3F 1F 00 3F 00 1F 00 1F 1F 00 00 00 00 1F 1F 3F 1F 1F 3F 00 00 3F 1F 00 3F 00 1F 00 1F 1F 00 00 00 00 1F 00 00 00 1F 3F 00 00 3F 1F 00 3F 00 1F 00 1F 1F 00 00 00 00 1F N.A. N.A. N.A. N.A. NTSC / PAL (mv) NTSC / PAL (IRE) 1211 130 1202 128 1065 109 948 93 939 92 699 58 995 99 923 89 797 72 725 62 608 45 535 35 411 18 338 7.3 634 49 392 15 384 14 267 -2.6 130 -22 122 -23 284 0 426 / 415 20 / 18 142 / 153 -20 / -19 0 -40 Note RGB values assume a 16 bpp color depth with 5-6-5 pixel packing. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 170 Epson Research and Development Vancouver Design Center 13.4.1 TV Image Display and Positioning This section describes how to setup and position an image to be displayed on a TV. Figure 13-4: "NTSC/PAL Image Positioning" shows an image positioned in the TV display with the related programmable parameters. The TV display area is shaded. The size of the display image determines the register values for the Horizontal Display Period, Horizontal Non-Display Period, Vertical Display Period, and Vertical Non-Display Period. The maximum and minimum values for these registers are given in Table 13-5, "Minimum and Maximum Values for NTSC/PAL TV," on page 171. The line period and frame period determined by these registers must also satisfy the following equations. NTSC: (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 6) = 910 ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) x 2 + 1) = 525 PAL: (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 7) = 1135 ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) x 2 + 1) = 625 The HRTC Start Position and VRTC Start Position registers position the image horizontally and vertically. The maximum and minimum register values for these registers are given in Table 13-5, "Minimum and Maximum Values for NTSC/PAL TV". Increasing the HRTC Start Position moves the image left, while increasing the VRTC Start Position moves the image up. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 171 t1 t6 Vertical Sync NTSC Odd Field 1 PAL Even Field 2,4 t4 / 2 t2 t3 t5 NTSC Odd Lines (1, 3, 5...) PAL Even Lines (2, 4, 6...) t6 Vertical Sync NTSC Even Field 2 PAL Odd Field 1,3 NTSC Even Lines (2, 4, 6...) PAL Odd Lines (1, 3, 5...) t5 + 1TLINE t4 / 2 t3 0 Horizontal Sync 909 (NTSC) 1134 (PAL) Figure 13-4: NTSC/PAL Image Positioning The maximum Horizontal and Vertical Display Widths shown in Table 13-5, "Minimum and Maximum Values for NTSC/PAL TV" include display areas that are normally hidden by the edges of the TV. The visible display dimensions are shown in Figure 13-5: "Typical Display Dimensions and Visible Display Dimensions for NTSC and PAL" as a guideline. The actual visible display area for a particular television may differ slightly from those dimensions given. Table 13-6, "Register Values for Example NTSC/PAL Images" lists some register values for some example images. Table 13-5 : Minimum and Maximum Values for NTSC/PAL TV Symbol t1 t2 t3 t4 t5 t6 Parameter TV Horizontal Non-Display Period TV Horizontal Display Width TV HRTC Start Position TV Vertical Display Height TV Vertical Non-Display Period TV Vertical Start Position Register(s) 52 50 53 57, 56 58 59 NTSC min max 158 510 400 752 25 t2 - 158 270 484 20 (21) 127 (128) 0 t5 - 20 PAL min 215 624 25 370 26 (27) 0 max 511 920 t2 - 215 572 127 (128) t5 - 26 Units T4SC T4SC T4SC TLINE TLINE TLINE Note The TV Vertical Non-Display Period (t5) varies by 1 line depending on the field that it follows. Note For NTSC panels the minimum and maximum values will vary for each application. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 172 Epson Research and Development Vancouver Design Center Total Display 752 x 484 Total Display 920 x 572 Visible Display 696 x 436 Visible Display 856 x 518 NTSC PAL Figure 13-5: Typical Display Dimensions and Visible Display Dimensions for NTSC and PAL Note For most implementations, the visible display does not equal the total display. The total display dimensions and the visible display dimensions must be determined for each specific implementation. Table 13-6 : Register Values for Example NTSC/PAL Images Parameter TV Horizontal Display Width TV Horizontal Non-Display Period TV HRTC Start Position TV Vertical Display Height TV Vertical Non-Display Period TV Vertical Start Position Register 50 52 53 57 56 58 59 NTSC PAL 752x484 696x436 640x480 920x572 856x518 800x572 640x480 5Dh 56h 4Fh 72h 6Ah 63h 4Fh 13h 1Ah 21h 1Ah 22h 29h 3Dh 02h 04h 09h 02h 05h 09h 15h 01h 01h 01h 02h 02h 02h 01h E3h B3h DFh 3Bh 05h 3Bh DFh 13h 2Bh 15h 19h 34h 19h 47h 00h 0Ch 00h 00h 0Dh 00h 17h 13.4.2 TV Cursor Operation See Section 14, "Ink Layer/Hardware Cursor Architecture" on page 173. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 173 14 Ink Layer/Hardware Cursor Architecture 14.1 Ink Layer/Hardware Cursor Buffers The Ink Layer/Hardware Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor. There may be several Ink Layer/Hardware Cursor images stored in the display buffer but only one may be active at any given time. The active Ink Layer/Hardware Cursor buffer is selected by the Ink/Cursor Start Address register (REG[071h] for LCD, REG[081h] for CRT/TV). This register defines the start address for the active Ink/Cursor buffer. The Ink/Cursor buffer must be positioned where it does not conflict with the image buffer and dual panel buffer. The start address for the Ink/Cursor buffer is programmed as shown in the following table. Table 14-1 : Ink/Cursor Start Address Encoding Ink/Cursor Start Address Bits [7:0] 0 Start Address (Bytes) 1280K - 1024 Comments This default value is suitable for a Hardware Cursor when there is no dual panel buffer. These positions can be used to: * position an Ink Layer buffer at the top of the display buffer; * position an Ink Layer buffer between the image and dual panel buffers; * position a Hardware Cursor buffer between the image and dual panel buffers; * select from a multiple of Hardware Cursor buffers. n = 160...1 1280K (n x 8192) n = 255...161 Invalid The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to the starting word of line n+1 is calculated as follows: LCD Ink Address Offset (words) = REG[032h] + 1 CRT/TV Ink Address Offset (words) = REG[050h] + 1 LCD or CRT/TV Cursor Address Offset (words) = 8 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 174 Epson Research and Development Vancouver Design Center 14.2 Ink/Cursor Data Format The Ink/Cursor image is always 2 bit-per-pixel. The following diagram shows the Ink/Cursor data format for a little endian system. 2-bpp: Byte 0 Byte 1 bit 7 A0 A4 B0 B4 A1 A5 B1 B5 A2 A6 B2 B6 A3 A7 bit 0 B3 B7 P0 P1 P2 P3 P4 P5 P6 P7 Pn = (An, Bn) Panel Display Host Address Ink/Cursor Buffer Figure 14-1: Ink/Cursor Data Format The image data for pixel n, (An,Bn), selects the color for pixel n as follows. Table 14-2 : Ink/Cursor Color Select (An,Bn) 00 Color Color 0 Comments Ink/Cursor Color 0 Register, (REG[078h], REG[077h], REG[076h] for LCD, REG[088h], REG[087h], REG[086h] for CRT/TV) Ink/Cursor Color 1 Register, (REG[07Ah], REG[07Bh],REG[07Ah] for LCD, REG[08Ah], REG[08Bh], REG[08Ah] for CRT/TV) Ink/Cursor is transparent - show background Ink/Cursor is transparent - show inverted background 01 10 11 Color 1 Background Inverted Background S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 175 14.3 Ink/Cursor Image Manipulation 14.3.1 Ink Image The Ink image should always start at the top left pixel (i.e. Cursor X Position and Cursor Y Position registers should always be set to zero). The width and height of the ink image are automatically calculated to completely cover the display. 14.3.2 Cursor Image The Cursor image size is always 64 x 64 pixels. The Cursor X Position and Cursor Y Position registers specify the position of the top left pixel. The following diagram shows how to position an unclipped cursor. P(0;0) P(x;y) P(x+63;y) P(x;y+63) P(x+63;y+63) Figure 14-2: Unclipped Cursor Positioning where For LCD: x = (REG[073h] bits [1:0], REG[072h]) and REG[073h] bit 7 = 0 y = (REG[075h] bits [1:0], REG[074h]) and REG[075h] bit 7 = 0 For CRT/TV: x = (REG[083h] bits [1:0], REG[082h]) and REG[083h] bit 7 = 0 y = (REG[085h] bits [1:0], REG[084h]) and REG[085h] bit 7 = 0 Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 176 Epson Research and Development Vancouver Design Center The following diagram shows how to position a cursor that is clipped at the top and left sides of the display. P(-x;-y) P(0;0) P(63-x;63-y) Figure 14-3: Clipped Cursor Positioning where For LCD: x = (REG[073h] bits [1:0], REG[072h]) <= 63 and REG[073h] bit 7 = 1 y = (REG[075h] bits [1:0], REG[074h]) <= 63 and REG[075h] bit 7 = 1 For CRT/TV: x = (REG[083h] bits [1:0], REG[082h]) <= 63 and REG[083h] bit 7 = 1 y = (REG[085h] bits [1:0], REG[084h]) <= 63 and REG[085h] bit 7 = 1 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 177 15 SwivelViewTM 15.1 Concept Most computer displays are refreshed in landscape - from left to right and top to bottom. Computer images are stored in the same manner. SwivelView is designed to rotate the displayed image on an LCD by 90, 180, or 270 in a clockwise direction. 90 rotation is also available on CRT. The rotation is done in hardware and is transparent to the user for all display buffer reads and writes. By processing the rotation in hardware, SwivelView offers a performance advantage over software rotation of the displayed image. 15.2 90 SwivelView 90 SwivelView uses a 1024 x 1024 pixel virtual window. The following figures show how the display buffer memory map changes in 90 SwivelView. The display is refreshed in the following sense: C-A-D-B. The application image is written to the S1D13806 in the following sense: A-B-C-D. The S1D13806 rotates and stores the application image in the following sense: C-A-D-B, the same sense as display refresh. The user can read/write to the display buffer naturally, without the need to rotate the image first in software. The registers that control the panning and scrolling of the panel window are designed for a landscape window. However, it is still possible to pan and scroll the portrait window in 90 SwivelView, but the user must program these registers somewhat differently (See Section 15.2.1, "Register Programming" on page 178). Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 178 Epson Research and Development Vancouver Design Center 1024 pixels C A B display start address 1024 pixels W D 1024 pixels A portrait window H B portrait window W C H D Image seen by the user Rotated image in the display buffer Figure 15-1: Relationship Between Screen Image and 90 Rotated Image in the Display Buffer Note W is the width of the LCD panel/CRT in number of pixels, (or the height of the portrait window in number of lines). H is the height of the LCD panel/CRT in number of lines, (or the width of the portrait window in number of pixels). Note The image must be written with a 1024 pixel offset between adjacent lines (1024 bytes for 8 bpp color depth or 2048 bytes for 16 bpp color depth) and the display start address must be calculated (see below). 15.2.1 Register Programming Enabling 90 Rotation on CPU Read/Write to Display Buffer Set SwivelView Enable bits 1:0 to 01b. All CPU accesses to the display buffer are translated to provide 90 clockwise rotation of the display image. Memory Address Offset The LCD/CRT Memory Address Offset register (REG[046h], REG[047h] for LCD, or REG[066h], REG[067h] for CRT) must be set for a 1024 pixel offset: LCD/CRT Memory Address Offset (words) = 1024 for 16 bpp color depth = 512 for 8 bpp color depth S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 179 Display Start Address As seen in Figure 15-1: "Relationship Between Screen Image and 90 Rotated Image in the Display Buffer" on page 178, the Display Start Address is determined by the location of the image corner "C", and it is generally non-zero. The LCD/CRT Display Start Address register (REG[042h], REG[043h], REG[044h] for LCD, or REG[062h], REG[063h], REG[064h] for CRT) must be set accordingly. LCD/CRT Display Start Address (words) = (1024 - W) for 16 bpp color depth = (1024 - W) / 2 for 8 bpp color depth where W is the width of the panel in number of pixels. Horizontal Panning Horizontal panning is achieved by changing the LCD/CRT Display Start Address register: * Increase/decrease LCD/CRT Display Start Address register by 1024 (16 bpp color depth) or 512 (8 bpp color depth) pans the display window to the right/left by 1 pixel. The amount the display window can be panned to the right is limited to 1024 pixels and limited by the amount of physical memory installed. Vertical Scrolling Vertical scrolling is achieved by changing the LCD/CRT Display Start Address register and/or the LCD/CRT Pixel Panning register: * Increment/decrement LCD/CRT Display Start Address register in 8 bpp color depth scrolls the display window up/down by 2 lines. * Increment/decrement LCD/CRT Display Start Address register in 16 bpp color depth scrolls the display window up/down by 1 line. * Increment/decrement LCD/CRT Pixel Panning register in 8 bpp color depth scrolls the display window up/down by 1 line. 15.2.2 Physical Memory Requirement Because the user must now deal with a virtual image of 1024x1024, the amount of image buffer required for a particular display mode has increased. The minimum amount of image buffer required is: Minimum Required Image Buffer (bytes) = (1024 x H) x 2 for 16 bpp color depth = (1024 x H) for 8 bpp color depth where H is the height of the panel in number of lines. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 180 Epson Research and Development Vancouver Design Center This minimum amount is required to display a 90 SwivelView image without panning; scrolling, however, is permissible. The degree an image can be panned depends on the amount of physical memory installed and how much of that is used by the dual panel buffer, Ink Layer, or Hardware Cursor. An image cannot be panned outside the 1024x1024 virtual display. Often it cannot be panned within the entire virtual display because part of the virtual display memory may be taken up by the dual panel buffer, Ink Layer, Hardware Cursor, or even the CRT/TV display buffer. The dual panel buffer is used for dual panel mode and has the following memory requirements. Dual Panel Buffer (bytes) =(W x H) / 4 =(W x H) / 16 for color mode for monochrome mode where W is the width of the panel in number of pixels, and H is the height of the panel in number of lines. The dual panel buffer is always located at the end of the physical memory. The Hardware Cursor or Ink Layer also takes up memory. If this memory is > 1KB, it must be located at an 8KB boundary, otherwise it may be located at the last 1KB area. The Hardware Cursor or Ink Layer must not overlap the image buffer or the dual panel buffer. Even though the virtual display is 1024x1024 pixels, the actual panel window is always smaller. Thus it is possible for the display buffer to be smaller than the virtual display but large enough to fit both the required image buffer and the dual panel buffer. This situation limits the maximum "accessible" horizontal virtual size as follows. Maximum Accessible Horizontal Virtual Size (pixels) = (Physical Memory - Dual Panel Buffer - Ink Layer) / 2048 for 16 bpp color depth = (Physical Memory - Dual Panel Buffer - Ink Layer) / 1024 for 8 bpp color depth For example, a 800x600 TFT panel running a color depth of 16 bpp requires 1200K byte of image buffer, 0K byte of dual panel buffer memory and 0K byte of ink layer memory (ink layer is not supported in this configuration, see Table 15-1, "Memory Size Required for SwivelView 90 and 270," on page181) . The virtual display size is 2048x2048 = 2M byte. This display can still be supported by the 1280K embedded DRAM even though it is smaller than the 2M byte virtual display because the size of the embedded DRAM is larger than the 1200K byte minimum required image buffer. The maximum accessible horizontal virtual size is = (1280K byte - 0K byte - 0K byte) / 2048 = 640. The programmer therefore has room to pan the portrait window to the right by 640 - 600 = 40 pixels. The programmer also should not read/write to the memory beyond the maximum accessible horizontal virtual size because that memory is either reserved for the dual panel buffer or not associated with any real memory at all. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 181 The following table summarizes the SwivelView 90 and 270 memory requirements for different panel sizes and display modes. Note that the S1D13806 memory size is 1280K byte. The calculation of the minimum required image buffer size is based on the image buffer and the dual panel buffer only. As noted in the table, the memory requirements of the Hardware Cursor/Ink Layer are not taken into account. The Hardware Cursor requires 1K byte of memory and the 2-bit Ink Layer requires (W x H) / 4 bytes of memory. Both the Hardware cursor and Ink Layer must reside at 8K byte boundaries, but only one is supported at a time. The following table shows only one possible Hardware Cursor/Ink Layer location - at the highest possible 8K byte boundary below the dual panel buffer which is always at the top. Table 15-1 : Memory Size Required for SwivelView 90 and 270 Panel Size Panel Type Color 320 x 240 Single Mono Color Single Mono 640 x 480 Color Dual Mono Color Single Mono 800 x 600 Color Dual Mono Color Depth 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp1 8 bpp 16 bpp Image Buffer Size 240KB 480KB 240KB 480KB 480KB 960KB 480KB 960KB 480KB 960KB 480KB 960KB 600KB 1200KB 600KB 1200KB 600KB Not Supported 600KB 1200KB 117.19KB 29.30KB 0KB 117.19KB/1KB 75KB 18.75KB 0KB 75KB/1KB 1128KB/1200KB 1184KB/1256KB 1160KB/1279KB --/1279KB 1160KB/1279KB --/1279KB 1040KB/1160KB --/1248KB 1200KB/1279KB 0KB 18.75KB/1KB 1256KB/1279KB Dual Panel Buffer Size Ink/Cursor Buffer Size Ink/Cursor Location Note 1. 800x600 color 16bpp dual panel is not supported as there is not enough memory to support the Dual Panel Buffer. Note Where KB = 1024 bytes, and MB = 1024K bytes. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 182 Epson Research and Development Vancouver Design Center 15.2.3 Limitations The following limitations apply to 90 SwivelView: * Only 8/16 bpp color depths are supported - 4 bpp color depth is not supported. * Hardware cursor and ink images are not rotated - software rotation must be used. SwivelView Enable bit 0 must be set to 0 when the user is accessing the Hardware Cursor or the Ink Layer buffer. * For 90 SwivelView modes, BitBLT (Bit Block Transfer) operations are still supported. However, the BitBLT data must first be rotated by software. For further information, refer to the S1D13806 Programmers Notes And Examples, document number X28B-G-003-xx. 15.3 180 SwivelView 180 SwivelView is where the image is simply displayed 180 clockwise rotated. For 180 SwivelView a virtual window is not required and all color depths (4/8/16 bpp) are supported. 15.3.1 Register Programming Reverse Display Buffer Fetching Address Direction Set SwivelView Enable bits 1:0 to 10b. During screen refresh, the direction of the address for display buffer fetching is reversed. This setting does not affect CPU to display buffer access in any way. Display Start Address The Display Start Address must be programmed to be at the bottom-right corner of the image, since the display is now refreshed in the reverse direction. The LCD Display Start Address register (REG[042h], REG[043h], REG[044h]) must be set accordingly. LCD Display Start Address (words) = (MA_Offset x H) - (MA_Offset - W) - 1 = (MA_Offset x H) - (MA_Offset - W/2) - 1 = (MA_Offset x H) - (MA_Offset - W/4) - 1 for 16 bpp color depth for 8 bpp color depth for 4 bpp color depth where H is the height of the panel in number of lines, W is the width of the panel in number of pixels, and MA_Offset is the LCD Memory Address Offset. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 183 Horizontal Panning Horizontal panning works in the same way as when SwivelView is not enabled, except that the effect of the LCD Pixel Panning register is reversed: * Increment/decrement LCD Display Start Address register pans the display window to the right/left. * Increment/decrement LCD Pixel Panning register pans the display window to the left/right. Vertical Panning Vertical panning works in the same way as when SwivelView is not enabled: * Increase/decrease LCD Display Start Address register by one memory address offset scrolls the display window down/up by 1 line. 15.3.2 Physical Memory Requirement 180 SwivelView mode requires the same physical memory as 0 SwivelView (un-rotated display). 15.3.3 Limitations The following limitations apply to 180 SwivelView: * Hardware Cursor and Ink Layer images are not rotated - software rotation must be used. * CRT/TV mode is not supported. * For 180 SwivelView modes, BitBLT (Bit Block Transfer) operations are supported normally. For further information, refer to the S1D13806 Programmers Notes And Examples, document number X28B-G-003-xx. 15.4 270 SwivelView 270 SwivelView is where the image is displayed 270 clockwise rotated. A 1024 x 1024 pixel virtual window is required as in 90 SwivelView. See Figure 15-1: "Relationship Between Screen Image and 90 Rotated Image in the Display Buffer" on page 178. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 184 Epson Research and Development Vancouver Design Center 15.4.1 Register Programming Enabling 270 Rotation on CPU Read/Write to Display Buffer Set SwivelView Enable bits 1:0 to 11b. The LCD Memory Address Offset register (REG[046h], REG[047h]) must be set for a 1024 pixel offset. LCD Memory Address Offset (words) = 1024 for 16 bpp color depth = 512 for 8 bpp color depth Display Start Address The Display Start Address must be programmed to be at the bottom-right corner of the image, since the display is now refreshed in the reverse direction. The LCD Display Start Address register (REG[042h], REG[043h], REG[044h]) must be set accordingly. LCD Display Start Address (words) = ((LCD Memory Address Offset) x H) - 1 where H is the height of the panel in number of lines. Horizontal Panning Horizontal panning is achieved by changing the LCD Display Start Address register. It works in the same way as in 90 SwivelView mode: * Increase/decrease LCD Display Start Address register by 1024 (16 bpp color depth) or 512 (8 bpp color depth) pans the display window to the right/left by 1 pixel. The amount the display window can be panned to the right is limited to 1024 pixels and limited by the amount of physical memory installed. Vertical Scrolling Vertical scrolling is achieved by changing the LCD Display Start Address register and/or the LCD Pixel Panning register. It works in the same way as in 90 SwivelView mode, except that the effect of the LCD Pixel Panning register is reversed: * Increment/decrement LCD Display Start Address register in 8 bpp color depth scrolls the display window up/down by 2 lines. * Increment/decrement LCD Display Start Address register in 16 bpp color depth scrolls the display window up/down by 1 line. * Increment/decrement LCD Pixel Panning register in 8 bpp color depth scrolls the display window down/up by 1 line. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 185 15.4.2 Physical Memory Requirement 270 SwivelView mode has the same physical memory requirement as in 90 SwivelView mode. See Section 15.2.2, "Physical Memory Requirement" on page 179. 15.4.3 Limitations The following limitations apply to 270 SwivelView: * Only 8/16 bpp color depths are supported - 4 bpp color depth is not supported. * Hardware Cursor and Ink Layer images are not rotated - software rotation must be used. SwivelView Enable bit 0 must be set to 0 when the user is accessing the Hardware Cursor or the Ink Layer memory. * CRT/TV mode is not supported. SwivelView Enable bit 0 must be set to 0 when the user is accessing the CRT/TV display buffer. * For 270 SwivelView modes, BitBLT (Bit Block Transfer) operations are still supported. However, the BitBLT data must first be rotated by software. For further information, refer to the S1D13806 Programmers Notes And Examples, document number X28B-G-003-xx. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 186 Epson Research and Development Vancouver Design Center 16 EPSON Independent Simultaneous Display (EISD) EPSON Independent Simultaneous Display (EISD) allows the S1D13806 to display independent images on two different displays (LCD panel and CRT or TV). 16.1 Registers The LCD panel timings and mode setup are programmed through the Panel Configuration Registers (REG[03Xh]) and the LCD Display Mode Registers (REG[04Xh]). The CRT/TV timings and mode setup are programmed through the CRT/TV Configuration Registers (REG[05Xh]) and the CRT/TV Display Mode Registers (REG[06Xh]). The Ink Layer or Hardware Cursor can also be independently controlled on the two displays. The LCD Ink/Cursor Registers (REG[07Xh]) control the Ink/Cursor on the LCD display; the CRT/TV Ink/Cursor Registers (REG[08Xh]) control the Ink/Cursor on the CRT or TV. Each display uses its own Look-Up Table (LUT), although there is only one set of LUT Registers (REG[1E0h], REG[1E2h], REG[1E4h]). Use the LUT Mode Register (REG[1E0h]) to select access to the LCD and/or CRT/TV LUTs. The pixel clock source for the two displays may be independent. Use the Clock Configuration Registers (REG[014h], REG[018h]) to select the LCD pixel clock source and the CRT/TV pixel clock source, respectively. Typically, CLKI2 is used for the CRT/TV display, while CLKI is used for the LCD display. Memory clock may come from CLKI or BUSCLK. 16.2 Display Mapping To display different images on the LCD and CRT/TV, the two images should reside in nonoverlapping areas of the display buffer, and the display start addresses point to the corresponding areas. The display buffer is mapped to the CPU address AB[20:0] linearly. The LCD and CRT/TV may display identical images by setting the display start addresses for the LCD and the CRT/TV to the same address. In this case only one image is needed in the display buffer. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 187 16.3 Bandwidth Limitation When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth available to the S1D13806. The result is that display modes with a high resolution or color depth may not be supported. In some cases, Ink Layers may not be possible on one or both of the displays. EISD increases the total demand for display refresh bandwidth and reduces CPU bandwidth, resulting in lower CPU performance. In a few cases when EISD is enabled, the default LCD and CRT/TV Display FIFO High Threshold Control register values are not optimally set, causing display problems with one or both of the displays. This condition may be corrected by adjusting the values of the LCD and CRT/TV Display FIFO High Threshold Control registers (REG[04Ah] for LCD and REG[06Ah] for CRT/TV). See Section 18.2, "Example Frame Rates" on page 192 for required FIFO settings. Changing this register to a non-zero value sets the high threshold FIFO level to this value. This register may not exceed 59 decimal. The high threshold FIFO level controls how often display fetch requests are issued by the FIFO. In general, a higher high threshold FIFO level increases the bandwidth to that display pipe, and a lower level reduces it. When the FIFO High Threshold Control register is set to 00h (default), the following settings are used: * 11h for 4 bpp color depth * 21h for 8 bpp color depth * 23h for 16 bpp color depth Most display problems may be corrected by increasing the associated high threshold FIFO level for that display. However, because the total available bandwidth is fixed, this change may create display problem for the other display. In this case, reducing the high threshold FIFO level for the other display instead may work. Sometimes, a combination of these two methods is required. Correcting EISD display problems by adjusting the FIFO High Threshold Control registers is mostly a trial-and-error process. Note While the user is free to experiment with these registers, recommended FIFO level settings for some of the more common EISD modes requiring non-default FIFO level settings are listed in Section 18.2, "Example Frame Rates" on page 192. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 188 Epson Research and Development Vancouver Design Center 17 MediaPlug Interface Winnov's MediaPlug Slave interface has been incorporated into the S1D13806. The MediaPlug Slave follows the Specification For Winnov MediaPlug Slave, Local module, Document Rev 0.3 with the following exceptions. 17.1 Revision Code The MediaPlug Slave Revision Code can be determined by reading bits 11:8 of the LCMD register. The revision code for this implementation is 0011b. 17.2 How to enable the MediaPlug Slave The MediaPlug Slave interface is enabled/disabled at the rising edge of RESET# by the state of CONF7. When CONF7 is set to 1, the MediaPlug functionality is enabled and GPIO12 is configured as the MediaPlug power control output pin (VMPEPWR) - see Table 4-9, "Summary of Power-On/Reset Options," on page 33. 17.3 MediaPlug Interface Pin Mapping The S1D13806 provides 8 pins for use by the MediaPlug interface (VMP[7:0]). GPIO12 is also used as the MediaPlug power control output pin (VMPEPWR) when the MediaPlug interface is enabled. The following table lists the MediaPlug pin mapping when the interface is enabled. Table 17-1: MediaPlug Interface Pin Mapping S1D13806 Pin Names VMP0 VMP1 VMP2 VMP3 VMP4 VMP5 VMP6 VMP7 GPIO12 IO Type O O IO IO IO IO I O O MediaPlug I/F VMPCLKN VMPCLK VMPD3 VMPD2 VMPD1 VMPD0 VMPRCTL VMPLCRL VMPEPWR Note VMPEPWR is controlled by bit 1 of the MediaPlug LCMD register. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 189 18 Clocking 18.1 Frame Rate Calculation 18.1.1 LCD Frame Rate Calculation The maximum LCD frame rate is calculated using the following formula. LPCLK max max. LCD Frame Rate = -------------------------------------------------------------------------------------------------------- LVDP + LVNDP ( LHDP + LHNDP ) x --------------n Where: LPCLKmax = maximum LCD pixel clock frequency LVDP = LCD Vertical Display Height = REG[039h] bits [1:0], REG[038h] bits [7:0] + 1 = LCD Vertical Non-Display Period = REG[03Ah] bits [5:0] + 1 = LCD Horizontal Display Width = ((REG[032h] bits [6:0]) + 1) x 8Ts = LCD Horizontal Non-Display Period = ((REG[034h] bits [4:0]) + 1) x 8Ts = minimum LCD pixel clock (LPCLK) period = 1 for single panel = 2 for dual panel LVNDP LHDP LHNDP Ts n Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 190 Epson Research and Development Vancouver Design Center 18.1.2 CRT Frame Rate Calculation The maximum CRT frame rate is calculated using the following formula. CPCLK max max. CRT Frame Rate = --------------------------------------------------------------------------------------------------------( CHDP + CHNDP ) x ( CVDP + CVNDP ) Where: CPCLKmax = maximum CRT pixel clock frequency CVDP = CRT Vertical Display Height = REG[057h] bits [1:0], REG[056h] bits [7:0] + 1 = CRT Vertical Non-Display Period = REG[058h] bits [6:0] + 1 = CRT Horizontal Display Width = ((REG[050h] bits [6:0]) + 1) x 8Ts = CRT Horizontal Non-Display Period = ((REG[052h] bits [5:0]) + 1) x 8Ts = minimum CRT pixel clock (CPCLK) period CVNDP CHDP CHNDP Ts S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 191 18.1.3 TV Frame Rate Calculation The maximum TV frame rate is calculated using the following formula. TPCLKmax max. TV Frame Rate = ----------------------------------------------------------------------------------------------------------------------TVDP ( THDP + THNDP ) x ---------------- + TVNDP + 0.5 2 Where: TPCLKmax = maximum TV pixel clock frequency TVDP = TV Vertical Display Height = REG[057h] bits [1:0], REG[056h] bits [7:0] + 1 = TV Vertical Non-Display Period = REG[058h] bits [6:0] + 1 = TV Horizontal Display Width = ((REG[050h] bits [6:0]) + 1) x 8Ts = TV Horizontal Non-Display Period = for NTSC output use ((REG[052h] bits [5:0]) x 8Ts) + 6 = for PAL output use ((REG[052h] bits [5:0]) x 8Ts) + 7 = minimum TV pixel clock (TPCLK) period TVNDP THDP THNDP Ts Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 192 Epson Research and Development Vancouver Design Center 18.2 Example Frame Rates For all example frame rates the following conditions apply: * Dual panel buffer is enabled for dual panel. * TV Flicker Filter is enabled for TV. * MCLK is 50MHz. 18.2.1 Frame Rates for 640x480 with EISD Disabled Table 18-1: Frame Rates for 640x480 with EISD Disabled LCD Type Ink No Passive Single / TFT Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink ------------------No No No No No No No No No Horiz Vert Res Res (pixels) bpp ------------------4 8 16 4 8 16 4 8 16 (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 ---------- 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 ---------- 4 8 16 4 8 16 4 8 16 4 8 16 4 8 16 4 8 16 ---------- 40 40 40 40 40 31 40 40 30 40 40 40 40 40 30 40 36 26 ---------- 56 64 64 64 72 72 64 72 64 56 64 64 64 72 64 64 72 56 ---------- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ---------- 119.5 118.1 118.1 235.8 233.1 181.0 235.8 233.1 176.8 119.5 118.1 118.1 235.8 233.1 176.8 235.8 209.8 155.0 ---------- ------------------CRT CRT CRT NTSC TV NTSC TV NTSC TV ------------------640 640 640 640 640 640 640 640 640 ------------------480 480 480 480 480 480 480 480 480 ------------------36 36 36 ------------------192 192 192 ------------------29 29 29 22 22 22 72 72 72 ------------------85.0 85.0 85.0 60 60 60 50 50 50 No No No Mono Passive Dual No No No Color Passive Dual No No Yes Passive Single / TFT Yes Yes Yes Mono Passive Dual Yes Yes Yes Color Passive Dual ------------------- Yes Yes ---------- 14.32 270 14.32 270 14.32 270 17.73 495 17.73 495 17.73 495 PAL TV PAL TV PAL TV Example Frame Rates with Ink Layer Enabled S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 193 Table 18-1: Frame Rates for 640x480 with EISD Disabled LCD Type ------------------- Ink ---------- Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink Yes Yes Yes Yes Yes Yes Yes Yes Yes Horiz Vert Res Res (pixels) bpp 4 8 16 4 8 16 4 8 16 (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) ---------- ---------- ---------- ---------- ---------- ---------- ---------- CRT CRT CRT NTSC TV NTSC TV NTSC TV 640 640 640 640 640 640 640 640 640 480 480 480 480 480 480 480 480 480 36 36 36 192 192 200 29 29 20 22 22 22 72 72 72 85.0 85.0 85.7 60 60 60 50 50 50 14.32 270 14.32 270 14.32 270 17.73 495 17.73 495 17.73 495 PAL TV PAL TV PAL TV Example Frame Rates with Ink Layer Enabled Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 194 Epson Research and Development Vancouver Design Center 18.2.2 Frame Rates for 800x600 with EISD Disabled Table 18-2: Frame Rates for 800x600 with EISD Disabled LCD Type Ink No No No Color Passive Dual TFT TFT 1 Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink Horiz Vert Res Res (pixels) bpp (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) TFT 800 800 800 800 800 800 800 800 800 800 ---- 600 600 600 600 600 600 600 600 600 600 ---- 8 16 4 8 16 8 16 4 8 16 ---- 65 44.4 40 40 30 65 40 38 36 26 ---- 232 160 64 72 64 232 144 64 72 56 ---- 35 35 1 1 1 35 35 1 1 1 ---- 99.2 72.8 153.8 152.4 115.3 99.2 66.7 146.1 137.2 100.9 ------CRT CRT CRT CRT CRT CRT CRT ---No No No No No No No Yes Yes Yes Yes Yes Yes Yes ---800 800 800 800 800 800 800 800 800 800 800 800 800 800 ---600 600 600 600 600 600 600 600 600 600 600 600 600 600 ---4 8 16 4 8 4 8 4 8 16 4 8 4 8 ---40 40 40 49.5 49.5 ---256 256 224 256 256 ---28 28 25 28 28 28 28 28 28 25 28 28 28 28 ---60.3 60.3 62.5 74.6 74.6 84.8 84.8 60.3 60.3 62.5 74.6 74.6 84.8 84.8 ---------------------------- No No Yes Yes Yes Yes Yes ---- Color Passive Dual ------- 56.25 256 56.25 256 40 40 40 49.5 49.5 256 256 224 256 256 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- CRT CRT CRT2 CRT CRT CRT CRT 56.25 256 56.25 256 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[07Eh] = 0Ch. 2. REG[08Eh] = 0Ah. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 195 18.2.3 Frame Rates for 1024x768 with EISD Disabled Table 18-3: Frame Rates for 1024x768 with EISD Disabled LCD Type TFT TFT ----1 Ink No Yes Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink Horiz Vert Res Res (pixels) bpp (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) 1024 1024 ----- 768 768 ----- 8 8 ----- 65 65 ----- 160 160 ----- 37 37 ----- 68.2 68.2 ----CRT CRT CRT CRT No No Yes Yes 1024 1024 1024 1024 768 768 768 768 4 8 4 8 65 65 65 65 320 320 320 320 41 41 41 41 59.8 59.8 59.8 59.8 ----- ----- Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[07Eh] = 0Ch. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 196 Epson Research and Development Vancouver Design Center 18.2.4 Frame Rates for LCD and CRT (640x480) with EISD Enabled Table 18-4: Frame Rates for LCD and CRT (640x480) with EISD Enabled LCD Type Ink No Passive Single Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Horiz Vert Res Res (pixels) bpp 16 16 4 8 16 8 8 4 8 4 8 8 8 8 16 8 16 8 8 16 8 4 8 16 8 8 8 (lines) PCLK( HNDP VNDP Frame Rate MHz) (pixels) (lines) (Hz) 320 640 640 640 640 800 1024 800 800 640 640 800 640 640 640 800 640 640 640 640 640 800 800 640 640 640 640 240 240 480 480 480 600 768 600 600 480 480 600 480 480 480 600 240 480 480 480 480 600 600 240 480 480 480 16 16 4 8 16 8 8 4 8 4 8 8 8 8 16 8 16 8 8 16 8 4 8 16 8 8 8 17 17 40 40 12 41 41 38 27.6 40 31.6 31.6 27.6 23.2 11.6 23.2 13.7 31.7 27.1 11 19 33.2 22.6 11.8 25.7 22.6 15 64 64 112 144 56 144 112 120 104 112 112 112 104 88 48 88 56 112 104 48 88 104 88 48 96 88 72 1 1 1 1 1 26 37 1 1 1 1 26 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 183.7 CRT 100.2 CRT 110.6 CRT 106.1 CRT 71.5 69.4 44.8 CRT CRT CRT 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 25.18 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 60.1 No No No Color Passive Dual No No No No No Yes Yes Yes Yes Yes Yes Yes No No No No No No No Yes Yes Yes Yes TFT TFT Color Passive Dual Passive Single 137.2 CRT 101.4 CRT 110.6 CRT 87.4 55.4 CRT CRT TFT Mono Passive Dual Color Passive Dual Color Passive Dual1 Color Passive Dual Passive Single2 Passive Single Mono Passive Dual2 Color Passive Dual Color Passive Dual Color Passive Dual2 Passive Single3 Passive Single Mono Passive Dual2 Color Passive Dual 153.9 CRT 132.2 CRT 70.0 86.8 81.7 87.6 CRT CRT CRT CRT 151.1 CRT 66.4 CRT 108.3 CRT 122.0 CRT 84.6 71.2 72.6 CRT CRT CRT 128.8 CRT 87.4 CRT Example Frame Rates with Ink Layer Enabled S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 197 Table 18-4: Frame Rates for LCD and CRT (640x480) with EISD Enabled LCD Type Color Passive Dual3 Color Passive Dual2 Ink Yes Yes Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink Yes Yes Horiz Vert Res Res (pixels) bpp 16 8 (lines) PCLK( HNDP VNDP Frame Rate MHz) (pixels) (lines) (Hz) 640 800 480 600 16 8 9.57 19.4 40 72 1 1 58.4 73.9 CRT CRT 640 640 480 480 25.18 25.18 160 160 44 44 60.1 60.1 Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[06Ah] = 3Ch. REG[06Bh] = 3Ch. 2. REG[08Eh] = 0Ch. 3. REG[06Ah] = 3Ch. REG[06Bh] = 3Ch. REG[07Eh] = 0Ch. REG[08Eh] = 0Ch. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 198 Epson Research and Development Vancouver Design Center 18.2.5 Frame Rates for LCD and CRT (800x600) with EISD Enabled Table 18-5: Frame Rates for LCD and CRT (800x600) with EISD Enabled LCD Type Passive Single Color Passive Dual Ink No No No No No No Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Horiz Vert Res Res (pixels) bpp 8 8 8 8 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) 640 640 640 800 800 800 640 640 640 640 640 640 640 640 800 640 640 640 640 240 480 480 600 600 600 240 480 480 480 240 480 480 480 600 240 480 480 480 8 8 8 8 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 34 34 22.5 34 38.6 22.5 26.2 26.2 22.5 19 24.4 24.4 20.6 17.2 17.2 19.8 19.8 17.2 14.7 120 120 88 120 112 88 96 96 88 72 88 88 80 64 64 72 72 64 56 1 1 1 28 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 185.6 CRT 93.0 CRT 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 60.3 128.2 CRT 58.8 84.2 74.0 CRT CRT CRT TFT1 Color Passive Dual Passive Single Mono Passive Dual Color Passive Dual2 Passive Single3 Passive Single Mono Passive Dual4 Color Passive Dual5 Passive Single3 Passive Single Mono Passive Dual6 Color Passive Dual6 140.6 CRT 147.7 CRT 128.2 CRT 110.7 CRT 139.1 CRT 69.7 CRT 118.7 CRT 101.4 CRT 66.1 CRT 115.4 CRT 57.8 CRT 101.4 CRT 87.6 CRT Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[04Ah] = 30h. REG[06Ah] = 30h. REG[04Bh] = 3Ch. REG[06Bh] = 3Ch. 2. REG[04Ah] = 1Ah. REG[06Bh] = 25h. 3. REG[06Ah] = 23h. REG[08Eh] = 0Ch. 4. REG[08Eh] = 0Ch. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 199 18.2.6 Frame Rates for LCD and CRT (1024x768) with EISD Enabled Table 18-6: Frame Rates for LCD and CRT (1024x768) with EISD Enabled LCD Type Passive Single1 Passive Single2 Passive Single Color Passive Dual2 Passive Single3 Passive Single Ink No No No No Yes Yes Yes Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink No No No No No No No Horiz Vert Res Res (pixels) bpp 8 8 8 8 8 8 8 (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) 320 640 640 640 320 640 640 240 240 480 480 240 240 480 8 8 8 8 8 8 8 31 21.1 21.1 13.8 16.2 16.2 20 144 80 80 56 56 56 72 1 1 1 1 1 1 1 277.2 CRT 121.6 CRT 60.9 82.3 CRT CRT 1024 1024 1024 1024 1024 1024 1024 768 768 768 768 768 768 768 65 65 65 65 65 65 65 320 320 320 320 320 320 320 41 41 41 41 41 41 41 59.8 59.8 59.8 59.8 59.8 59.8 59.8 178.8 CRT 96.6 58.4 CRT CRT Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[04Ah] = 25h. REG[04Bh] = 3Ch. REG[06Ah] = 30h. REG[06Bh] = 3Ch. 2. REG[04Ah] = 1Ah. REG[06Ah] = 30h. REG[06Bh] = 3Ch. 3. REG[07Eh] = 0Ch. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 200 Epson Research and Development Vancouver Design Center 18.2.7 Frame Rates for LCD and NTSC TV with EISD Enabled Table 18-7: Frame Rates for LCD and NTSC TV with EISD Enabled LCD Type Ink No Passive Single / TFT Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Horiz Vert Res Res (pixels) bpp 16 16 4 8 8 8 8 8 4 8 4 8 8 4 8 4 8 4 8 4 8 4 4 (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) 320 640 640 640 640 640 800 800 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 240 240 480 480 480 480 600 600 480 480 480 480 240 480 480 480 480 240 240 480 480 480 480 16 16 4 8 8 8 8 8 4 8 4 8 8 4 8 4 8 4 8 4 8 4 8 10.7 10.7 40 27.6 24 21.1 27.6 21.1 39 20.5 28.1 18.2 20.4 33.7 18.4 23.7 16 27.4 17.5 23.7 15.6 20.4 14.2 56 56 152 136 128 112 136 112 144 112 112 96 104 128 96 96 88 104 88 96 80 88 80 1 1 1 1 1 1 35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 118.1 63.8 105.0 73.9 129.6 116.4 46.4 76.9 103.4 113.1 155.0 102.6 113.8 91.2 103.7 133.6 91.2 152.8 99.7 133.6 89.9 116.3 81.8 NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 14.32 270 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 No No No Mono Passive Dual Color Passive Dual No No No No Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes NTSC TV NTSC TV NTSC TV TFT Color Passive Dual Passive Single Mono Passive Dual Color Passive Dual Passive Single Mono Passive Dual Color Passive Dual Passive Single Passive Single1 Mono Passive Dual Mono Passive Dual1 Color Passive Dual NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV NTSC TV Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[07Eh] = 0Ch. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 201 18.2.8 Frame Rates for LCD and PAL TV with EISD Enabled Table 18-8: Frame Rates for LCD and PAL TV with EISD Enabled LCD Type Ink No Passive Single Horiz Vert Res Res (pixels) (lines) max max min min Frame CRT/ bpp PCLK HNDP VNDP Rate TV (MHz) (pixels) (lines) (Hz) Ink No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Horiz Vert Res Res (pixels) bpp 16 16 4 8 8 8 8 8 4 8 4 8 8 4 4 8 4 8 4 8 4 8 4 4 (lines) PCLK HNDP VNDP Frame Rate (MHz) (pixels) (lines) (Hz) 320 640 640 640 640 640 800 800 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 240 240 480 480 480 480 600 600 480 480 480 480 240 480 480 480 480 480 240 240 480 480 480 480 16 16 4 8 8 8 8 8 4 8 4 8 8 4 4 8 4 8 4 8 4 8 4 8 7.5 9 40 25.8 22.2 19 43 19 37.2 19 26.2 16.3 18.1 31.7 26 16.1 22.7 13.9 21 15.4 22.7 13.9 19.6 12.3 40 40 152 128 120 104 136 104 144 104 104 88 96 120 112 88 96 72 96 80 96 72 80 64 1 1 1 1 1 1 35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 86.4 55.0 105.0 69.8 121.2 106.0 72.3 69.8 98.6 106.0 146.1 92.9 102.0 86.7 143.4 91.8 128.0 81.0 118.4 88.8 128.0 81.0 113.0 72.5 PAL TV PAL TV PAL TV PAL TV PAL TV 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 640 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 17.73 495 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 No No No Mono Passive No Dual Color Passive No Dual PAL TV TFT1 No PAL TV PAL TV Color Passive No Dual Passive Single Yes PAL TV Mono Passive Yes Dual2 Color Passive Yes Dual Yes Passive Single PAL TV PAL TV PAL TV PAL TV PAL TV PAL TV PAL TV PAL TV PAL TV PAL TV No No Mono Passive No Dual No Color Passive No Dual No Passive Single Passive Single2 Yes Yes PAL TV Mono Passive Yes Dual Mono Passive Yes Dual2 Color Passive Yes Dual Yes PAL TV PAL TV PAL TV PAL TV Example Frame Rates with Ink Layer Enabled The FIFO values for these display modes must be set as follows: 1. REG[04Ah] = 3Ch. REG[04Bh] = 3Ch. 2. REG[07Eh] = 7Ch. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 202 Epson Research and Development Vancouver Design Center 19 Power Save Mode The S1D13806 includes a software initiated power save mode designed for very low-power applications. In addition, the S1D13806 dynamically disables internal clock networks when not required. Similarly, the LCD and/or CRT/TV pipelines are shut down when not required for the selected display mode. For power save mode AC Timing, see Section 6.4.2, "Power Save Status" on page 63. 19.1 Overview Power save mode is initiated by setting REG[1F0h] bit 0 to 1. When power save mode is enabled the following conditions apply. * LCD display is disabled. * CRT/TV display is disabled. * Memory access is not allowed. * Memory is in self-refresh mode. * Register access is allowed. 19.2 Power Save Status Bits LCD Power Save Status bit The LCD Power Save Status bit (REG[1F1h] bit 0) indicates the state of the LCD panel. When this bit returns a 1, the panel is powered down. When this bit returns a 0, the panel is powered up, or in transition of powering up or down. The system may disable the LCD pixel clock source when this bit returns a 1. The LCD Power Save Status bit is set to 1 after chip reset. Memory Controller Power Save Status bit The Memory Controller Power Save Status bit (REG[1F1h] bit 1) indicates the state of the SDRAM interface. When this bit returns a 1, the SDRAM interface is powered down and the SDRAM is in self-refresh mode. This condition occurs shortly after power save mode is invoked. When this bit returns a 0, the SDRAM interface is active. The system may disable the memory clock source when this bit returns a 1. The Memory Controller Power Save Status bit is set to 0 after chip reset. S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 203 19.3 Power Save Mode Summary Table 19-1: Power Save Mode Summary Function LCD Display Active? CRT/TV Display Active? Register Access Possible? Memory Access Possible? LCD LUT Access Possible? CRT/TV LUT Access Possible? LCD interface CRT/TV interface SDRAM interface Host Interface LCD Disabled no -Yes Yes Yes -Forced Low -Active Active 1 CRT/TV Disabled -no Yes Yes -Yes -Disabled Active Active 2 Power Save Mode Enabled No No Yes No Yes Yes Forced Low Disabled Self-Refresh Active Note 1. LCD pixel clock required. Note 2. CRT/TV pixel clock required. Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 204 Epson Research and Development Vancouver Design Center 20 Mechanical Data 22.0 0.4 20.0 108 0.1 73 109 72 0.1 Index 144 37 1 0.5 1.4 0.1 +0.1 0.2 -0.05 36 20.0 1.7 max 0.125-0.025 0 10 0.5 0.2 +0.05 0.1 1.0 All dimensions in mm Figure 20-1: Mechanical Drawing 144-pin QFP20 S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 22.0 0.4 Epson Research and Development Vancouver Design Center Page 205 140.2 1.4max 0.40.05 TOP VIEW 140.2 0.1max SIDE VIEW 0.50.05 0.08 M 1 T P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 All dimensions in mm BOTTOM VIEW Figure 20-2: Mechanical Drawing 220-pin PFBGA Hardware Functional Specification Issue Date: 02/04/10 1 S1D13806 X28B-A-001-12 0.8 R Page 206 Epson Research and Development Vancouver Design Center 21 References The following documents contain additional information related to the S1D13806. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Electronics America website at www.eea.epson.com or the Epson Research and Development Website at www.erd.epson.com. * 13806CFG Configuration Utility Users Manual (X28B-B-001-xx) * 13806SHOW Demonstration Program Users Manual (X28B-B-002-xx) * 13806PLAY Diagnostic Utility Users Manual (X28B-B-003-xx) * 13806BMP Demonstration Program Users Manual (X28B-B-004-xx) * 13806FILT Test Utility Users Manual (X28B-B-005-xx) * 13806SWIVEL Demonstration Utility Users Manual (X28B-B-006-xx) * S1D13806 Product Brief (X28B-C-001-xx) * S1D13806 Windows CE v2.x Display Driver (X28B-E-001-xx) * S1D13806 Wind River WindML v2.0 Display Driver (X28B-E-002-xx) * S1D13806 Wind River UGL v1.2 Display Driver (X28B-E-003-xx) * S1D13806 Linux Console Driver (X28B-E-004-xx) * S1D13806 QNX Photon v2.0 Display Driver (X28B-E-005-xx) * S1D13806 Windows CE v3.x Display Driver (X28B-E-006-xx) * S1D13806 Programming Notes And Examples (X28B-G-003-xx) * S5U13806B00C Rev. 1.0 Evaluation Board User Manual (X28B-G-004-xx) * Interfacing to the PC Card Bus (X28B-G-005-xx) * S1D13806 Power Consumption (X28B-G-006-xx) * Interfacing to the NEC VR4102/VR4111 Microprocessors (X28B-G-007-xx) * Interfacing to the Motorola MPC821 Microprocessor (X28B-G-008-xx) * Interfacing to the Philips MIPS PR31500/PR31700 Microprocessors (X28B-G-009-xx) * Interfacing to the Toshiba MIPS TX3912 Microprocessor (X28B-G-010-xx) * Interfacing to the NEC VR4121 Microprocessor (X28B-G-011-xx) * Interfacing to the StrongArm SA-1110 Microprocessor (X28B-G-012-xx) * S1D13806 Register Summary (X28B-R-001-xx) S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 Epson Research and Development Vancouver Design Center Page 207 22 Sales and Technical Suppor t Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/ Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/ Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de Hardware Functional Specification Issue Date: 02/04/10 S1D13806 X28B-A-001-12 Page 208 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13806 X28B-A-001-12 Hardware Functional Specification Issue Date: 02/04/10 |
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